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    Segmented thick film resistors
    81.
    发明授权
    Segmented thick film resistors 失效
    分段厚膜电阻

    公开(公告)号：US5621240A

    公开(公告)日：1997-04-15

    申请号：US523580

    申请日：1995-09-05

    Applicant: Marion E. Ellis

    Inventor： Marion E. Ellis

    IPC: H01C7/00 ,  H01C17/00 ,  H01C17/22 ,  H01L27/01 ,  H01L27/04

    CPC classification number: H01C17/003 ,  H01C17/22 ,  Y10S257/904

    Abstract: A novel thick film resistor configuration and a method for fabricating thick film resistors, by which such resistors can be processed to achieve targeted electrical properties in an as-fired condition. The configuration and method of this invention involve creating a thick film resistor in the form of a series of short resistors whose combined resistance values approximately equal the predetermined resistance value required of the thick film resistor by its hybrid electronic circuit, yet with the use of minimal post-firing trimming. Such a configuration and method enable the production of thick film resistors from the same ink composition but with significantly different aspect ratios, yet which exhibit minimal differences between TCR values. Consequently, thick film resistors configured and fabricated in accordance with this invention are characterized by enhanced production throughput, repeatability, and reliability.

    Abstract translation: 一种新颖的厚膜电阻器结构和一种制造厚膜电阻器的方法，通过该方法可以处理这种电阻器以在烧制条件下实现目标电性能。 本发明的结构和方法包括制造一系列短电阻器形式的厚膜电阻器，其组合电阻值大约等于其混合电子电路所需的厚膜电阻器的预定电阻值，但是使用最小 后烧烤修剪 这种配置和方法使得能够从相同的油墨组合物生产厚膜电阻器，但具有显着不同的纵横比，但是它们在TCR值之间表现出最小的差异。 因此，根据本发明构造和制造的厚膜电阻的特征在于增强的生产量，重复性和可靠性。

    Dielectric as load resistor in 4T SRAM
    82.
    发明授权
    Dielectric as load resistor in 4T SRAM 失效
    介质作为4T SRAM中的负载电阻

    公开(公告)号：US5616951A

    公开(公告)日：1997-04-01

    申请号：US519066

    申请日：1995-08-24

    Applicant: Mong-Song Liang

    Inventor： Mong-Song Liang

    IPC: H01L21/8244 ,  H01L27/11

    CPC classification number: H01L27/11 ,  H01L27/1112 ,  Y10S257/904 ,  Y10S438/954

    Abstract: A method of for manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises formation of a first polysilicon layer on the semiconductor substrate, patterning and etching the first polysilicon layer, formation of an interpolysilicon layer over the first polysilicon layer, patterning and etching an opening through the interpolysilicon layer exposing a contact area on the surface of the first polysilicon layer, forming a dielectric load resistor in the opening upon the contact area on the first polysilicon layer, and formation of a second polysilicon layer on the device over the dielectric load resistor, over the interpolysilicon layer.

    Abstract translation: 一种用于在包括具有电阻器的SRAM单元的半导体衬底上制造半导体器件的方法，包括在半导体衬底上形成第一多晶硅层，图案化和蚀刻第一多晶硅层，在第一多晶硅层上形成多晶硅层 ，通过所述多晶硅层图案化和蚀刻暴露所述第一多晶硅层表面上的接触区域的开口，在所述第一多晶硅层上的所述接触区域上的所述开口中形成介电负载电阻器，以及在所述第一多晶硅层上形成第二多晶硅层 在介质负载电阻上，在多晶硅层之上。

    Semiconductor device having electrically coupled transistors with a differential current gain
    83.
    发明授权
    Semiconductor device having electrically coupled transistors with a differential current gain 失效
    具有具有差分电流增益的电耦合晶体管的半导体器件

    公开(公告)号：US5616948A

    公开(公告)日：1997-04-01

    申请号：US459198

    申请日：1995-06-02

    Applicant: James R. Pfiester

    Inventor： James R. Pfiester

    IPC: H01L27/11 ,  H01L29/76

    CPC classification number: H01L27/1108 ,  H01L27/11 ,  Y10S257/903 ,  Y10S257/904

    Abstract: A semiconductor device includes a pass transistor (28) electrically coupled to a driver transistor (16) by a common drain region (52). The pass transistor (28) includes the pass gate electrode (44) having a polycrystalline silicon layer (68). The driver transistor (16) includes a driver gate electrode (40) having a polycrystalline silicon layer (74). The dopant concentration in polycrystalline silicon layer (74) is greater than the dopant concentration in polycrystalline silicon layer (68). The differential and dopant concentration between the pass gate electrode (44) and the driver gate electrode (40) results in a greater current gain in the driver transistor (16) relative to the pass transistor (28). When incorporated into an SRAM memory cell (10), the driver transistor (16) and the pass transistor (28) provide greater cell stability by improving the immunity of the cell to electrical disturbance through the pass transistor (28).

    Abstract translation: 半导体器件包括通过公共漏极区（52）电耦合到驱动晶体管（16）的通过晶体管（28）。 传输晶体管（28）包括具有多晶硅层（68）的通过栅电极（44）。 驱动晶体管（16）包括具有多晶硅层（74）的驱动栅电极（40）。 多晶硅层（74）中的掺杂剂浓度大于多晶硅层（68）中的掺杂剂浓度。 传导栅电极（44）与驱动栅电极（40）之间的差分和掺杂浓度导致驱动晶体管（16）中相对于传输晶体管（28）的电流增益更大。 当结合到SRAM存储单元（10）中时，驱动晶体管（16）和通过晶体管（28）通过改善电池对通过晶体管（28）的电气干扰的抗扰度来提供更大的电池稳定性。

    Split polysilicon SRAM cell
    85.
    发明授权
    Split polysilicon SRAM cell 失效
    分离多晶硅SRAM单元

    公开(公告)号：US5569962A

    公开(公告)日：1996-10-29

    申请号：US341940

    申请日：1994-11-16

    Applicant: Ming-Tzong Yang

    Inventor： Ming-Tzong Yang

    IPC: H01L21/8244 ,  H01L27/11 ,  H01L23/48 ,  H01L29/78

    CPC classification number: H01L27/1108 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/90 ,  Y10S257/904

    Abstract: An SRAM semiconductor device comprises a first layer, a second layer and a third layer of polysilicon are separated by dielectric layers formed on a substrate, and a split gate structure with transistors formed in different polysilicon levels. Preferably, the split gate structure includes pull down transistors and pass gate transistors formed in different polysilicon levels; the second polysilicon layer extends into contact with the substrate; the second polysilicon layer contacts the third polysilicon layer in an interconnection region; and the third polysilicon layer comprises a polysilicon load resistor.

    Abstract translation: 包括第一层，第二层和第三多晶硅层的SRAM半导体器件由形成在衬底上的电介质层分离，并且具有以不同多晶硅层形成的晶体管的分离栅极结构。 优选地，分离栅极结构包括形成在不同多晶硅层中的下拉晶体管和栅极晶体管; 第二多晶硅层延伸成与基板接触; 第二多晶硅层在互连区域中接触第三多晶硅层; 并且第三多晶硅层包括多晶硅负载电阻器。

    Semiconductor memory device and the manufacturing method thereof
    88.
    发明授权
    Semiconductor memory device and the manufacturing method thereof 失效
    半导体存储器件及其制造方法

    公开(公告)号：US5436506A

    公开(公告)日：1995-07-25

    申请号：US134815

    申请日：1993-10-12

    Applicant: Han-soo Kim ,  Kyung-tae Kim

    Inventor： Han-soo Kim ,  Kyung-tae Kim

    IPC: H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  H01L27/02 ,  H01L29/04

    CPC classification number: H01L27/11 ,  H01L27/1108 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

    Abstract: An SRAM memory cell structure is provided which has the access transistor gates formed from a different layer than that of the word line. The first access transistor gate of a first memory cell is connected to the first access transistor gate of an adjacent second memory cell, and a second access transistor gate of the first memory cell is connected to a second access transistor gate of an third oppositely adjacent memory cell. Each pair of coupled gates are formed separate from the access transistor gates in adjacent memory cells. The word lines connect the separated access transistor gates. The word lines are formed on an insulating layer above the gates of the access transistors. The word lines are, however, electrically connected to the gates of the access transistors through contact holes formed in the insulating layer. Each memory cell is arranged symmetrically with respect to an adjacent memory cell, and the components of each memory cell are symmetrical. Therefore, a structure and a method for a reduction in the area of an SRAM cell of the conventional circuit design is provided, resulting in a larger layout margin and a more reliable and more highly integrated SRAM device.

    Abstract translation: 提供了一种SRAM存储单元结构，其具有由与字线不同的层形成的存取晶体管栅极。 第一存储单元的第一存取晶体管栅极连接到相邻第二存储单元的第一存取晶体管栅极，第一存储单元的第二存取晶体管栅极连接到第三相对相邻存储器的第二存取晶体管栅极 细胞。 每对耦合栅极与相邻存储单元中的存取晶体管栅极分离形成。 字线连接分离的存取晶体管栅极。 字线形成在存取晶体管的栅极上方的绝缘层上。 然而，字线通过形成在绝缘层中的接触孔电连接到存取晶体管的栅极。 每个存储单元相对于相邻的存储单元对称布置，并且每个存储单元的分量是对称的。 因此，提供了用于减小常规电路设计的SRAM单元的面积的结构和方法，导致更大的布局裕度和更可靠且更高度集成的SRAM器件。

    Semiconductor device
    89.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US5396105A

    公开(公告)日：1995-03-07

    申请号：US941325

    申请日：1992-09-04

    Applicant: Takeo Nakayama

    Inventor： Takeo Nakayama

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/10 ,  H01L27/11 ,  H01L27/02 ,  G11C11/00 ,  H01L23/48 ,  H01L29/04

    CPC classification number: H01L27/1112 ,  H01L2924/0002 ,  Y10S257/904

    Abstract: A MOSFET constituting a flip-flop circuit and a MOSFET for control of reading and writing data out of and into a memory cell are formed on a semiconductor. The gate electrode of the first MOSFET and the gate electrode of the second MOSFET are formed by layers of different levels. The gate electrodes have an overlapped portion R. The first and second MOSFETs are arranged symmetrically with respect to a certain point P. By virtue of the above structure, the degree of integration of a static RAM is enhanced.

    Abstract translation: 构成触发电路的MOSFET和用于控制读出数据到存储单元的数据的MOSFET形成在半导体上。 第一MOSFET的栅电极和第二MOSFET的栅电极由不同电平的层形成。 栅电极具有重叠部分R.第一和第二MOSFET相对于某一点P对称地布置。由于上述结构，静态RAM的集成度增强。

    Active device constructed in opening formed in insulation layer and process for making same
    90.
    发明授权
    Active device constructed in opening formed in insulation layer and process for making same 失效
    在绝缘层中形成的开口中构造的有源器件及其制造方法

    公开(公告)号：US5391505A

    公开(公告)日：1995-02-21

    申请号：US147290

    申请日：1993-11-01

    Applicant: Ashok K. Kapoor

    Inventor： Ashok K. Kapoor

    IPC: H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L21/266

    CPC classification number: H01L29/6675 ,  H01L27/1108 ,  H01L29/7833 ,  Y10S257/904

    Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.

    Abstract translation: 至少部分地，在形成MOS型有源器件的第一源极/漏极区域的半导体衬底的一部分之上的绝缘层（例如氧化物层）中的开口中至少部分地构造小型MOS型有源器件。 在开口的侧壁上并且与形成器件的第一源极/漏极区域的衬底的部分电连通的半导体材料包括MOS器件的沟道部分。 与沟道的相对端连通的第二源极/漏极区域形成在与开口相邻并且与开口中的沟道材料电连通的绝缘层上。 栅极氧化物层形成在通道部分上并且至少部分地在开口中，并且然后在栅极氧化物上方形成导电栅电极。

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