公开(公告)号：US06835979B1

公开(公告)日：2004-12-28

申请号：US09591968

申请日：2000-06-12

申请人： David K. Liu ,  Ting-wah Wong

发明人： David K. Liu ,  Ting-wah Wong

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/42328 ,  H01L29/7885

摘要： A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.

摘要翻译： 高度可伸缩的非易失性存储单元包括形成在三阱中的单元。 选择晶体管可以具有也用作横向双极晶体管的发射极的源极。 横向双极晶体管用作电荷注入器。 电荷注入器提供电子用于衬底热电子注入到浮动栅极上用于编程。 可以通过在所述感测晶体管的源极和沟道之间的衬底上形成作为控制栅极的延伸的电容器来扩展电解槽耗尽/反转区域。

公开(公告)号：US06800894B1

公开(公告)日：2004-10-05

申请号：US09459305

申请日：1999-12-10

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11543

摘要： Certain embodiments include a semiconductor device capable of preventing a retardation of signal transmission between the smallest units, a method for the manufacture thereof, a circuit substrate and an electronic device. Embodiments also include a manufacturing method comprising a laminating step of forming tunnel insulating films 12 and 22, floating gates 14 and 24, dielectric films 16 and 26, control gates 18 and 28 on first and second memory cell areas 10 and 20 formed mutually adjacent to each other on a semiconductor substrate 30, a plurality of impurity area formation steps of forming sources and drains 32, 34, 36 and 38 on the first and second memory cell areas 10 and 20, and forming a connecting area 40 capable of forming an electric connection between one 32 of the source and drain of the first memory cell area 10 and one 36 of the source and drain of the second memory cell area 20. The connecting area 40 is formed to have a lower electric resistance than impurity areas 42 and 44 formed in one of the of impurity area formation steps.

摘要翻译： 某些实施例包括能够防止最小单元之间的信号传输延迟的半导体器件，其制造方法，电路基板和电子器件。 实施例还包括一种制造方法，其包括在第一和第二存储单元区域10和20上相互相邻形成隧道绝缘膜12和22，浮栅14和24，介电膜16和26，控制栅极18和28的层压步骤 彼此在半导体衬底30上，多个杂质区形成步骤，在第一和第二存储单元区域10和20上形成源极和漏极32,34,36和38，并形成能够形成电气的连接区域40 第一存储单元区域10的源极和漏极中的一个32与第二存储单元区域20的源极和漏极之间的一个36的连接。连接区域40形成为具有比杂质区域42和44更低的电阻 形成在杂质区域形成步骤之一中。

公开(公告)号：US06794711B2

公开(公告)日：2004-09-21

申请号：US10620025

申请日：2003-07-14

申请人： Sung-taeg Kang ,  Jeong-uk Han ,  Soeng-gyun Kim

发明人： Sung-taeg Kang ,  Jeong-uk Han ,  Soeng-gyun Kim

IPC分类号： H01L29788

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

摘要： Non-volatile memory devices according to embodiments of the invention can include, for example, a semiconductor substrate, a source region, a drain region, an impurity region, a vertical structure, a control gate insulating layer, a control gate electrode, a gate insulating layer, and a gate electrode. The impurity region is in a floating state between the source region and the drain region. The vertical structure is formed of a tunneling layer, a charge trapping layer, and a blocking layer sequentially stacked between the source region and the impurity region. The control gate insulating layer is between the source region and the impurity region and adjacent to the vertical structure. The control gate electrode is formed on the vertical structure and the control gate insulating layer. The gate insulating layer is between the impurity region and the drain region. The gate electrode is formed on the gate insulating layer.

摘要翻译： 根据本发明的实施例的非易失性存储器件可以包括例如半导体衬底，源极区，漏极区，杂质区，垂直结构，控制栅极绝缘层，控制栅电极，栅极 绝缘层和栅电极。 杂质区域在源极区域和漏极区域之间处于浮置状态。 垂直结构由依次层叠在源极区域和杂质区域之间的隧道层，电荷俘获层和阻挡层形成。 控制栅极绝缘层位于源极区域和杂质区域之间并且与垂直结构相邻。 控制栅电极形成在垂直结构和控制栅极绝缘层上。 栅极绝缘层位于杂质区域和漏极区域之间。 栅电极形成在栅绝缘层上。

公开(公告)号：US06791141B1

公开(公告)日：2004-09-14

申请号：US09172096

申请日：1998-10-13

申请人： J. Dennis Keller ,  Roger R. Lee

发明人： J. Dennis Keller ,  Roger R. Lee

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/4925

摘要： Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.

摘要翻译： 描述了浮栅晶体管及其形成方法。 在一个实施方式中，在衬底上形成浮栅。 浮动门具有内部第一部分和外部第二部分。 在内部第一部分中提供增强电导的杂质以比外部第二部分中的增强电导率的杂质更大的浓度。 在另一实施方案中，浮栅由第一导电掺杂半导体材料层和基本上未掺杂的半导体材料的第二层形成。 在另一实施方案中，浮栅由具有第一平均晶粒尺寸的第一材料和具有大于第一平均晶粒尺寸的第二平均晶粒尺寸的第二材料形成。

公开(公告)号：US06784484B2

公开(公告)日：2004-08-31

申请号：US10131923

申请日：2002-04-25

申请人： Pieter Blomme ,  Bogdan Govoreanu ,  Maarten Rosmeulen

发明人： Pieter Blomme ,  Bogdan Govoreanu ,  Maarten Rosmeulen

IPC分类号： H01L29788

CPC分类号： H01L29/513 ,  B82Y10/00 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28273 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7883 ,  H01L29/7885

摘要： An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.

摘要翻译： 公开了在第一导电区域和第二导电区域之间延伸的绝缘屏障。 提供绝缘屏障用于将电荷载体从第一区域延伸到第二区域，绝缘屏障包括接触第一区域的第一部分和接触第一部分并朝第二区域延伸的第二部分，第一部分基本上比 第二部分，第一部分构造在第一电介质中，第二部分构造在不同于第一电介质的第二电介质中，第一电介质具有比第二电介质低的介电常数。

公开(公告)号：US06770933B2

公开(公告)日：2004-08-03

申请号：US10316471

申请日：2002-12-11

申请人： Jozef C. Mitros

发明人： Jozef C. Mitros

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/66825

摘要： A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well (220). The semiconductor substrate (210) is doped with a first type dopant, and the well (220) is doped with a second type dopant opposite to that of the first type dopant. The semiconductor device (200) also comprises first and second electrodes (310, 320), wherein at least the first electrodes (310) are located over the well (220) and first dielectric (250). A second dielectric (510) may be located between the first and second electrodes (310, 320).

摘要翻译： 一种半导体器件（200），包括具有位于其中的阱（220）的半导体衬底（210）和位于所述阱（220）上方的第一电介质（250）。 半导体衬底（210）掺杂有第一类型掺杂剂，并且阱（220）掺杂有与第一类型掺杂剂相反的第二类型掺杂剂。 半导体器件（200）还包括第一和第二电极（310,320），其中至少第一电极（310）位于阱（220）和第一电介质（250）之上。 第二电介质（510）可以位于第一和第二电极（310,320）之间。

公开(公告)号：US06765267B2

公开(公告)日：2004-07-20

申请号：US10248413

申请日：2003-01-17

申请人： Han-Chung Lai

发明人： Han-Chung Lai

IPC分类号： H01L29788

CPC分类号： H01L27/124 ,  G03F7/70633 ,  H01L23/544 ,  H01L27/1288 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A pixel structure comprising a thin film transistor, a pixel electrode, a scan line, a data line and an alignment mark. The alignment mark is formed beneath the data line. Misalignment is assessed through the degree of shifting between the alignment mark and the data line relative to each other. In addition, misalignment is also gauged through the degree of shifting between the alignment mark and the channel layer within the thin film transistor relative to each other.

摘要翻译： 包括薄膜晶体管，像素电极，扫描线，数据线和对准标记的像素结构。 在数据线之下形成对准标记。 通过相对于彼此的对准标记和数据线之间的移动程度来评估未对准。 此外，还通过薄膜晶体管内的对准标记和沟道层之间的相对于彼此的移动程度来测量未对准。

公开(公告)号：US06765259B2

公开(公告)日：2004-07-20

申请号：US10233310

申请日：2002-08-28

申请人： Jongoh Kim

发明人： Jongoh Kim

IPC分类号： H01L29788

CPC分类号： H01L27/11568 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/0692 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory (NVM) array including a plurality of 2-bit NVM transistors arranged in a plurality of rows extending along a first axis, and a plurality of columns extending along a second axis, perpendicular to the first axis. The non-volatile memory array includes a plurality of field isolation regions located in a semiconductor substrate and a plurality of word lines extending over the semiconductor substrate along the first axis, wherein the word lines form control gates of the 2-bit NVM transistors. Oxide-nitride-oxide (ONO) structures are formed between the substrate and the word lines, wherein the nitride layer provides floating gate storage for the NVM transistors. A plurality of H-shaped source/drain regions are defined by the field isolation regions and the word lines, wherein each source/drain region serves as a source/drain for four different NVM transistors in the array.

摘要翻译： 一种非易失性存储器（NVM）阵列，包括排列成沿着第一轴延伸的多行的多个2位NVM晶体管和沿第二轴线垂直于第一轴线延伸的多个列。 非易失性存储器阵列包括位于半导体衬底中的多个场隔离区域和沿着第一轴线在半导体衬底上延伸的多个字线，其中字线形成2位NVM晶体管的控制栅极。 在衬底和字线之间形成氧化氮化物 - 氧化物（ONO）结构，其中氮化物层为NVM晶体管提供浮动栅极存储。 多个H形源极/漏极区域由场隔离区域和字线限定，其中每个源极/漏极区域用作阵列中的四个不同NVM晶体管的源极/漏极。

公开(公告)号：US06737702B1

公开(公告)日：2004-05-18

申请号：US10626089

申请日：2003-07-24

申请人： Chun Jiang ,  Sunil Mehta ,  Stewart Logie

发明人： Chun Jiang ,  Sunil Mehta ,  Stewart Logie

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/115 ,  H01L27/11558

摘要： A zero power memory cell includes first and second NMOS transistors and a PMOS transistor, wherein the first NMOS transistor and first PMOS transistor each include a three-implant channel region, and wherein the second NMOS transistor further includes a two-implant channel region.

摘要翻译： 零功率存储单元包括第一和第二NMOS晶体管和PMOS晶体管，其中第一NMOS晶体管和第一PMOS晶体管各自包括三注入沟道区，并且其中第二NMOS晶体管还包括双注入沟道区。

公开(公告)号：US06737700B1

公开(公告)日：2004-05-18

申请号：US10249864

申请日：2003-05-13

申请人： Ko-Hsing Chang ,  Cheng-Yuan Hsu

发明人： Ko-Hsing Chang ,  Cheng-Yuan Hsu

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： A non-volatile memory cell having a symmetric cell structure is disclosed. The non-volatile memory cell includes a substrate, a tunnel oxide layer, two floating gates, a dielectric layer, a plurality of spacers, a control gate, and two split gates. The substrate has at least two sources and a drain that is located between the sources. The floating gates are formed on the tunneling oxide layer, and each of floating gates is located between each source and the drain. The dielectric layer is formed on the floating gates. The control gate is formed over the drain and is between the floating gates. The split gates are located adjacent to outward sidewalls of the floating gates, respectively. Therefore, each of the split gates is opposite to the control gate through each of the floating gates.

摘要翻译： 公开了具有对称单元结构的非易失性存储单元。 非易失性存储单元包括衬底，隧道氧化物层，两个浮动栅极，电介质层，多个间隔物，控制栅极和两个分离栅极。 衬底具有至少两个源和位于源之间的漏极。 浮动栅极形成在隧道氧化物层上，每个浮栅位于每个源极和漏极之间。 电介质层形成在浮栅上。 控制栅极形成在漏极之上并且在浮动栅极之间。 分流门分别位于浮动门的外侧壁附近。 因此，每个分离门通过每个浮动栅极与控制栅极相对。