公开(公告)号：US06265266B1

公开(公告)日：2001-07-24

申请号：US08722596

申请日：1996-09-27

申请人： Anders T. Dejenfelt ,  Kameswara K. Rao ,  George H. Simmons ,  Tomoyuki Furuhata

发明人： Anders T. Dejenfelt ,  Kameswara K. Rao ,  George H. Simmons ,  Tomoyuki Furuhata

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： A two-transistor flash EPROM cell for high-speed high-density PLD applications is provided. The two-transistor cell includes a storage transistor connected in series to an access transistor. The storage transistor prevents problems associated with both over-erase and punch-through, and allows for scaling of the gate length to realize 5V cell programming.

摘要翻译： 提供了用于高速高密度PLD应用的双晶体管闪存EPROM单元。 双晶体管单元包括与存取晶体管串联连接的存储晶体管。 存储晶体管防止与过擦除和穿通相关的问题，并允许缩放栅极长度以实现5V单元编程。

公开(公告)号：US06249021B1

公开(公告)日：2001-06-19

申请号：US09308993

申请日：1999-08-24

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L2972

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7883

摘要： A nonvolatile semiconductor memory device comprising: a semiconductor substrate (20); and a memory transistor (100) including a source region (20S) and a drain region (20D) which are impurity diffusion layers formed in the semiconductor substrate, a tunnel insulating layer (25) formed on the semiconductor substrate, and a staked-structure gate electrode (20G) having a floating gate (24), a dielectric layer (23) and a control gate (22) which are layered on the tunnel insulating layer. The floating gate (24) is formed of a polysilicon layer having an impurity concentration of 1×1019 to 1×1020 cm−3. Denoting the impurity concentration of a polysilicon layer constituting the floating gate (24) as CFG and the impurity concentration of a polysilicon layer constituting the control gate (22) as CCG, it is preferable that the following relational expression (1) be satisfied: 0.3×CFG≦CCG≦0.8×CFG In the nonvolatile semiconductor memory device in the present invention, an impurity concentration of the polysilicon layer constituting the floating gate is in a specific range for preventing deterioration of the film quality of the tunnel insulating layer due to impurities contained in the floating gate, thereby making it possible to enhance characteristics such as an erase characteristic and a data retaining characteristic.

摘要翻译： 一种非易失性半导体存储器件，包括：半导体衬底（20）; 以及存储晶体管（100），其包括作为形成在所述半导体衬底中的杂质扩散层的源极区（20S）和漏极区（20D），形成在所述半导体衬底上的隧道绝缘层（25） 栅极电极（20G），其具有浮置栅极（24），电介质层（23）和控制栅极（22），层叠在隧道绝缘层上。 浮置栅极（24）由杂质浓度为1×1019至1×1020cm-3的多晶硅层形成。 将构成浮栅（24）的多晶硅层的杂质浓度表示为CFG，构成控制栅（22）的多晶硅层的杂质浓度为CCG，则优选满足以下关系式（1）： 本发明的非易失性半导体存储器件中，构成浮置栅极的多晶硅层的杂质浓度处于特定范围内，以防止由于浮动栅极中包含的杂质导致的隧道绝缘层的膜质量劣化，从而使其 可以增强诸如擦除特性和数据保持特性的特性。

公开(公告)号：US5315150A

公开(公告)日：1994-05-24

申请号：US797919

申请日：1991-11-26

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L21/8249 ,  H01L21/336 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L21/22

CPC分类号： H01L29/0847 ,  H01L21/743 ,  H01L21/76895 ,  H01L2924/0002

摘要： A semiconductor device including a MOS element having a buried contact structure. The buried contact structure includes a first contact diffused region formed by diffusion from a polycrystalline silicon layer and a second contact diffused region formed by diffusion deeper than the first contact diffused region, so that a parasitic resistance of the MOS element can be reduced. In a composite element composed of the MOS element and a bipolar element, partly since the first contact diffused region and an emitter diffused region of the bipolar element can be formed simultaneously, and partly since the depth of connection of the emitter diffused region, with the parasitic resistance of the MOS element being reduced, it is possible to realize a high-speed operation.

摘要翻译： 一种包括具有埋入接触结构的MOS元件的半导体器件。 掩埋接触结构包括通过从多晶硅层的扩散形成的第一接触扩散区域和通过比第一接触扩散区域更深的扩散而形成的第二接触扩散区域，从而可以降低MOS元件的寄生电阻。 在由MOS元件和双极元件构成的复合元件中，部分由于双极元件的第一接触扩散区域和发射极扩散区域可以同时形成，并且部分由于发射极扩散区域的连接深度与 MOS元件的寄生电阻降低，可以实现高速运转。

公开(公告)号：US5250447A

公开(公告)日：1993-10-05

申请号：US744853

申请日：1991-08-14

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L21/205 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L21/265 ,  H01L27/02

CPC分类号： H01L29/66272 ,  H01L21/8249

摘要： A semiconductor device in which both a bipolar element and a MOS element are formed on a single semiconductor substrate. This device is composed of a semiconductor substrate, a bipolar element formed on the substrate so as to insulate a base region and an emitter electrode from one another by a base/emitter electrode insulating film, and a MOS element formed on the substrate in such a manner that a gate electrode together with an emitter electrode of the bipolar element are formed in a common layer and that a gate oxide film is formed between the gate electrode and another layer adjacent to and under the first-named layer. The base/emitter electrode insulating film has a thickness greater than that of the gate oxide film.

摘要翻译： 在单个半导体衬底上形成双极性元件和MOS元件的半导体器件。 该器件由半导体衬底，在衬底上形成的双极性元件构成，以便通过基极/发射极电极绝缘膜将基极区域和发射极彼此绝缘，并且在该衬底上形成的MOS元件 将栅电极与双极型元件的发射电极一起形成在公共层中，并且在栅极电极与邻接于第一命名层的另一层之间形成栅极氧化膜的方式。 基极/发射极电极绝缘膜的厚度大于栅极氧化膜的厚度。

公开(公告)号：US07972917B2

公开(公告)日：2011-07-05

申请号：US12492080

申请日：2009-06-25

申请人： Tomoyuki Furuhata ,  Hideyuki Akanuma ,  Hiroaki Nitta

发明人： Tomoyuki Furuhata ,  Hideyuki Akanuma ,  Hiroaki Nitta

IPC分类号： H01L21/8238

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A method for manufacturing a semiconductor device is disclosed. The method includes: forming a LDMOS region, an offset drain MOS region, and a CMOS region; simultaneously forming a first well in the LDMOS region and the offset drain MOS region; simultaneously forming a second well in the first well of the LDMOS region and the CMOS region; and forming a second well in the CMOS region, wherein a depth of the first well is larger than a depth of the second well and the second well is a retrograde well formed by a high energy ion implantation method.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括：形成LDMOS区域，偏移漏极MOS区域和CMOS区域; 同时在LDMOS区域和偏移漏极MOS区域形成第一阱; 同时在LDMOS区域和CMOS区域的第一阱中形成第二阱; 以及在所述CMOS区域中形成第二阱，其中所述第一阱的深度大于所述第二阱的深度，并且所述第二阱是通过高能离子注入方法形成的逆行阱。

公开(公告)号：US07026685B2

公开(公告)日：2006-04-11

申请号：US10873596

申请日：2004-06-21

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L27/115

摘要： Semiconductor devices including a non-volatile memory transistor and methods for manufacturing such semiconductor devices are described. One semiconductor device may include a silicon substrate 10, a floating gate 22 disposed above the silicon substrate 10 through a first dielectric layer 20, a second dielectric layer 26 that contacts at least a part of the floating gate 22, a control gate 28 formed over the second dielectric layer 26, and a source region 14 and a drain region 16 formed in the silicon substrate 10. A wiring layer 40 is provided above the floating gate 22, and the entirety of the floating gate 22 is overlapped by the wiring layer 40 as viewed in a plan view.

公开(公告)号：US06921964B2

公开(公告)日：2005-07-26

申请号：US10072658

申请日：2002-02-07

申请人： Tomoyuki Furuhata ,  Kotaro Misawa

发明人： Tomoyuki Furuhata ,  Kotaro Misawa

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L29/7885 ,  H01L21/28273 ,  H01L29/42324

摘要： A semiconductor device includes a non-volatile memory transistor 100. An interlayer dielectric layer 40 is provided on a semiconductor layer 10 where the non-volatile memory transistor 100 is formed. The interlayer dielectric layer 40 is an insulation layer for electrically isolating a conductive layer 30 formed over the semiconductor layer 10 from the non-volatile memory transistor, and includes a layer 42 containing nitride.

摘要翻译： 半导体器件包括非易失性存储晶体管100。 在形成非易失性存储晶体管100的半导体层10上设置层间介质层40。 层间介质层40是用于将形成在半导体层10上的导电层30与非易失性存储晶体管电隔离的绝缘层，并且包括含有氮化物的层42。

公开(公告)号：US06812519B2

公开(公告)日：2004-11-02

申请号：US10014584

申请日：2001-12-14

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L2976

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L27/115

摘要： Semiconductor devices including a non-volatile memory transistor and methods for manufacturing such semiconductor devices are described. One semiconductor device may include a silicon substrate 10, a floating gate 22 disposed above the silicon substrate 10 through a first dielectric layer 20, a second dielectric layer 26 that contacts at least a part of the floating gate 22, a control gate 28 formed over the second dielectric layer 26, and a source region 14 and a drain region 16 formed in the silicon substrate 10. A wiring layer 40 is provided above the floating gate 22, and the entirety of the floating gate 22 is overlapped by the wiring layer 40 as viewed in a plan view.

摘要翻译： 描述了包括非易失性存储晶体管的半导体器件及其制造方法。 一个半导体器件可以包括硅衬底10，通过第一电介质层20设置在硅衬底10上方的浮置栅极22，与浮栅22的至少一部分相接触的第二电介质层26， 第二电介质层26以及形成在硅衬底10中的源极区14和漏极区16.布线层40设置在浮置栅极22的上方，并且整个浮栅22与布线层40重叠 如平面图所示。

公开(公告)号：US06673678B2

公开(公告)日：2004-01-06

申请号：US09956893

申请日：2001-09-21

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L2130

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： The method of manufacturing a non-volatile semiconductor memory device comprises a step of providing a first ion implantation on the principal surface of a silicon substrate in a manner to cover a groove to form a first impurity region on the principal surface. Next, a step of providing a second ion implantation to cover the groove to form a second impurity region on the principal surface that overlaps the first impurity region at the groove and electrically connects the second source/drain region and the third source/drain region by the first impurity region. In short, the impurity region at the groove is formed by a twice ion implantation of the first and second ion implantations.

摘要翻译： 制造非易失性半导体存储器件的方法包括以覆盖沟槽的方式在硅衬底的主表面上提供第一离子注入以在主表面上形成第一杂质区的步骤。 接下来，提供第二离子注入以覆盖沟槽以在主表面上形成与沟槽处的第一杂质区域重叠的第二杂质区域并将第二源极/漏极区域和第三源极/漏极区域电连接的第二离子注入步骤 第一杂质区。 简而言之，通过第一和第二离子注入的两次离子注入形成凹槽处的杂质区域。

公开(公告)号：US06337250B2

公开(公告)日：2002-01-08

申请号：US09155357

申请日：1999-03-08

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/823425 ,  H01L27/0705 ,  H01L27/115 ,  H01L27/11524

摘要： A method of fabricating a semiconductor device including MOS elements comprising the steps of forming: a gate insulation layer on a semiconductor substrate; forming a gate electrode on the gate insulation layer; and implanting impurity ions into source and drain forming regions, wherein the ion implantation into said source and drain forming regions is performed in separate ion implantation steps. In at least either one of the ion implantation steps for the source forming region or for the drain forming region, a resist layer used for blocking impurities is provided with a wall extending to said gate insulation layer at a location distant from said gate electrode, said wall allowing charges to flow to the substrate. In accordance with the method provided herein, a semiconductor device having excellent data retention characteristics can be provided based on a simple process and without creating additional fabrication steps, while avoiding quality degradation of the tunnel oxide layer or the gate oxide layer resulting from charge-up at the time of ion implantation.

摘要翻译： 一种制造包括MOS元件的半导体器件的方法，包括以下步骤：在半导体衬底上形成栅极绝缘层; 在栅极绝缘层上形成栅电极; 以及将杂质离子注入源极和漏极形成区域，其中在分离的离子注入步骤中进行到所述源极和漏极形成区域的离子注入。 在用于源极形成区域或漏极形成区域的离子注入步骤中的至少一个中，用于阻挡杂质的抗蚀剂层设置有在远离所述栅极电极的位置延伸到所述栅极绝缘层的壁，所述壁 允许电荷流到基底的壁。 根据本文提供的方法，可以基于简单的工艺提供具有优异的数据保存特性的半导体器件，而不产生额外的制造步骤，同时避免由充电引起的隧道氧化物层或栅极氧化物层的质量劣化 在离子注入时。