公开(公告)号：US06265266B1

公开(公告)日：2001-07-24

申请号：US08722596

申请日：1996-09-27

申请人： Anders T. Dejenfelt ,  Kameswara K. Rao ,  George H. Simmons ,  Tomoyuki Furuhata

发明人： Anders T. Dejenfelt ,  Kameswara K. Rao ,  George H. Simmons ,  Tomoyuki Furuhata

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： A two-transistor flash EPROM cell for high-speed high-density PLD applications is provided. The two-transistor cell includes a storage transistor connected in series to an access transistor. The storage transistor prevents problems associated with both over-erase and punch-through, and allows for scaling of the gate length to realize 5V cell programming.

摘要翻译： 提供了用于高速高密度PLD应用的双晶体管闪存EPROM单元。 双晶体管单元包括与存取晶体管串联连接的存储晶体管。 存储晶体管防止与过擦除和穿通相关的问题，并允许缩放栅极长度以实现5V单元编程。

公开(公告)号：US06249021B1

公开(公告)日：2001-06-19

申请号：US09308993

申请日：1999-08-24

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L2972

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7883

摘要： A nonvolatile semiconductor memory device comprising: a semiconductor substrate (20); and a memory transistor (100) including a source region (20S) and a drain region (20D) which are impurity diffusion layers formed in the semiconductor substrate, a tunnel insulating layer (25) formed on the semiconductor substrate, and a staked-structure gate electrode (20G) having a floating gate (24), a dielectric layer (23) and a control gate (22) which are layered on the tunnel insulating layer. The floating gate (24) is formed of a polysilicon layer having an impurity concentration of 1×1019 to 1×1020 cm−3. Denoting the impurity concentration of a polysilicon layer constituting the floating gate (24) as CFG and the impurity concentration of a polysilicon layer constituting the control gate (22) as CCG, it is preferable that the following relational expression (1) be satisfied: 0.3×CFG≦CCG≦0.8×CFG In the nonvolatile semiconductor memory device in the present invention, an impurity concentration of the polysilicon layer constituting the floating gate is in a specific range for preventing deterioration of the film quality of the tunnel insulating layer due to impurities contained in the floating gate, thereby making it possible to enhance characteristics such as an erase characteristic and a data retaining characteristic.

摘要翻译： 一种非易失性半导体存储器件，包括：半导体衬底（20）; 以及存储晶体管（100），其包括作为形成在所述半导体衬底中的杂质扩散层的源极区（20S）和漏极区（20D），形成在所述半导体衬底上的隧道绝缘层（25） 栅极电极（20G），其具有浮置栅极（24），电介质层（23）和控制栅极（22），层叠在隧道绝缘层上。 浮置栅极（24）由杂质浓度为1×1019至1×1020cm-3的多晶硅层形成。 将构成浮栅（24）的多晶硅层的杂质浓度表示为CFG，构成控制栅（22）的多晶硅层的杂质浓度为CCG，则优选满足以下关系式（1）： 本发明的非易失性半导体存储器件中，构成浮置栅极的多晶硅层的杂质浓度处于特定范围内，以防止由于浮动栅极中包含的杂质导致的隧道绝缘层的膜质量劣化，从而使其 可以增强诸如擦除特性和数据保持特性的特性。

公开(公告)号：US5315150A

公开(公告)日：1994-05-24

申请号：US797919

申请日：1991-11-26

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L21/8249 ,  H01L21/336 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L21/22

CPC分类号： H01L29/0847 ,  H01L21/743 ,  H01L21/76895 ,  H01L2924/0002

摘要： A semiconductor device including a MOS element having a buried contact structure. The buried contact structure includes a first contact diffused region formed by diffusion from a polycrystalline silicon layer and a second contact diffused region formed by diffusion deeper than the first contact diffused region, so that a parasitic resistance of the MOS element can be reduced. In a composite element composed of the MOS element and a bipolar element, partly since the first contact diffused region and an emitter diffused region of the bipolar element can be formed simultaneously, and partly since the depth of connection of the emitter diffused region, with the parasitic resistance of the MOS element being reduced, it is possible to realize a high-speed operation.

摘要翻译： 一种包括具有埋入接触结构的MOS元件的半导体器件。 掩埋接触结构包括通过从多晶硅层的扩散形成的第一接触扩散区域和通过比第一接触扩散区域更深的扩散而形成的第二接触扩散区域，从而可以降低MOS元件的寄生电阻。 在由MOS元件和双极元件构成的复合元件中，部分由于双极元件的第一接触扩散区域和发射极扩散区域可以同时形成，并且部分由于发射极扩散区域的连接深度与 MOS元件的寄生电阻降低，可以实现高速运转。

公开(公告)号：US5250447A

公开(公告)日：1993-10-05

申请号：US744853

申请日：1991-08-14

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L21/205 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L21/265 ,  H01L27/02

CPC分类号： H01L29/66272 ,  H01L21/8249

摘要： A semiconductor device in which both a bipolar element and a MOS element are formed on a single semiconductor substrate. This device is composed of a semiconductor substrate, a bipolar element formed on the substrate so as to insulate a base region and an emitter electrode from one another by a base/emitter electrode insulating film, and a MOS element formed on the substrate in such a manner that a gate electrode together with an emitter electrode of the bipolar element are formed in a common layer and that a gate oxide film is formed between the gate electrode and another layer adjacent to and under the first-named layer. The base/emitter electrode insulating film has a thickness greater than that of the gate oxide film.

摘要翻译： 在单个半导体衬底上形成双极性元件和MOS元件的半导体器件。 该器件由半导体衬底，在衬底上形成的双极性元件构成，以便通过基极/发射极电极绝缘膜将基极区域和发射极彼此绝缘，并且在该衬底上形成的MOS元件 将栅电极与双极型元件的发射电极一起形成在公共层中，并且在栅极电极与邻接于第一命名层的另一层之间形成栅极氧化膜的方式。 基极/发射极电极绝缘膜的厚度大于栅极氧化膜的厚度。

公开(公告)号：US08330219B2

公开(公告)日：2012-12-11

申请号：US12492082

申请日：2009-06-25

申请人： Tomoyuki Furuhata ,  Hideyuki Akanuma ,  Hiroaki Nitta

发明人： Tomoyuki Furuhata ,  Hideyuki Akanuma ,  Hiroaki Nitta

IPC分类号： H01L29/66

CPC分类号： H01L29/7816 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368

摘要： A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.

摘要翻译： 半导体器件包括：具有第一导电类型的半导体衬底; 具有第二导电类型并设置在半导体衬底内的阱; 具有第一导电类型并设置在该阱内的第一杂质区; 具有第二导电类型的第二杂质区，设置在阱内并远离第一杂质区; 以及设置在所述阱周围并远离所述第二杂质区域的具有第一导电类型的第三杂质区域。 在该半导体器件中，在半导体衬底的厚度方向上，阱形成为比第一杂质区域，第二杂质区域和第三杂质区域更深; 并且所述第一杂质区域和所述第二杂质区域之间的最小距离小于所述第二杂质区域和所述第三杂质区域之间的最小距离。

公开(公告)号：US20050023598A1

公开(公告)日：2005-02-03

申请号：US10873596

申请日：2004-06-21

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L27/115

摘要： Semiconductor devices including a non-volatile memory transistor and methods for manufacturing such semiconductor devices are described. One semiconductor device may include a silicon substrate 10, a floating gate 22 disposed above the silicon substrate 10 through a first dielectric layer 20, a second dielectric layer 26 that contacts at least a part of the floating gate 22, a control gate 28 formed over the second dielectric layer 26, and a source region 14 and a drain region 16 formed in the silicon substrate 10. A wiring layer 40 is provided above the floating gate 22, and the entirety of the floating gate 22 is overlapped by the wiring layer 40 as viewed in a plan view.

摘要翻译： 描述了包括非易失性存储晶体管的半导体器件及其制造方法。 一个半导体器件可以包括硅衬底10，通过第一电介质层20设置在硅衬底10上方的浮置栅极22，与浮栅22的至少一部分相接触的第二电介质层26， 第二电介质层26以及形成在硅衬底10中的源极区14和漏极区16.布线层40设置在浮置栅极22的上方，并且整个浮栅22与布线层40重叠 如平面图所示。

公开(公告)号：US06756629B1

公开(公告)日：2004-06-29

申请号：US09599477

申请日：2000-06-23

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L2976

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/7885

摘要： Embodiments include a semiconductor device including a non-volatile memory transistor with a split-gate structure that is operable at a lower voltage. The semiconductor device includes a P-type silicon substrate 10 that includes a memory region 4000, an N-type first well 11 located in the memory region 4000, and a P-type second well located in the first well 11. The semiconductor device includes a non-volatile memory transistor with a split-gate structure. A source 16 and a drain 14 of the non-volatile memory transistor are located in the second well 12. The silicon substrate 10 and the second well 12 are isolated from each other by the first well 11. Therefore, the potential of the second well 12 can be set independently of the potential of the silicon substrate 11.

摘要翻译： 实施例包括半导体器件，其包括具有可在较低电压下操作的分离栅极结构的非易失性存储晶体管。 半导体器件包括P型硅衬底10，其包括存储区域4000，位于存储区域4000中的N型第一阱11和位于第一阱11中的P型第二阱。半导体器件包括 具有分离栅结构的非易失性存储晶体管。 非易失性存储晶体管的源极16和漏极14位于第二阱12中。硅衬底10和第二阱12由第一阱11彼此隔离。因此，第二阱的电位 12可以独立于硅衬底11的电位来设置。

公开(公告)号：US06717204B1

公开(公告)日：2004-04-06

申请号：US09604702

申请日：2000-06-23

申请人： Tomoyuki Furuhata ,  Atsushi Yamazaki

发明人： Tomoyuki Furuhata ,  Atsushi Yamazaki

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/42324

摘要： Embodiments include a semiconductor device having a non-volatile memory transistor, the semiconductor device including a plurality of field effect transistors operated at a plurality of different voltage levels. The semiconductor device has a memory region 4000, and first second and third transistor regions 1000, 2000 and 3000 respectively including field effect transistors that operate at different voltage levels. The memory region 4000 includes a split-gate non-volatile memory transistor 400. The first transistor region 1000 includes a first voltage-type transistor 100 that operates at a first voltage level. The second transistor region 2000 includes a second voltage-type transistor 200 that operates at a to second voltage level. The third transistor region 3000 includes a third voltage-type transistor that operates at a third voltage level. The second voltage-type transistor 200 has a gate insulation layer 22 that is formed from at least two insulation layers 22a and 22b. The insulation layer 22b is formed in the same step in which a gate insulation layer 20 of the first voltage-type transistor 100 is formed.

摘要翻译： 实施例包括具有非易失性存储晶体管的半导体器件，该半导体器件包括以多个不同电压电平工作的多个场效应晶体管。 半导体器件具有存储区域4000，以及分别包括在不同电压电平下工作的场效应晶体管的第一和第三晶体管区域1000,2000和3000。 存储区域4000包括分闸非易失性存储晶体管400.第一晶体管区域1000包括在第一电压电平下操作的第一电压型晶体管100。 第二晶体管区域2000包括工作在第二电压电平的第二电压型晶体管200。 第三晶体管区域3000包括在第三电压电平下操作的第三电压型晶体管。 第二电压型晶体管200具有由至少两个绝缘层22a和22b形成的栅极绝缘层22。 在形成第一电压型晶体管100的栅极绝缘层20的相同步骤中形成绝缘层22b。

公开(公告)号：US06696340B2

公开(公告)日：2004-02-24

申请号：US10042140

申请日：2002-01-11

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L21336

CPC分类号： H01L29/7886 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11543 ,  H01L29/42324

摘要： A method for manufacturing a semiconductor device having a non-volatile memory transistor may include the steps of forming a floating gate 22 over a semiconductor layer 10 through a first insulation layer 20, forming a second insulation layer 26 that contacts the floating gate 22, forming a control gate 28 over the second insulation layer 26, forming a source region 14 and a drain region 16 in the semiconductor layer 10, depositing a insulation layer 40 over the semiconductor layer 10, and etching the insulation layer 40 to form a sidewall insulation layer, wherein the etching of the insulation layer 40 is conducted such that the insulation layer 40 remains above the floating gate 40, and the floating gate 22 is not exposed.

摘要翻译： 具有非易失性存储晶体管的半导体器件的制造方法可以包括以下步骤：通过第一绝缘层20在半导体层10上形成浮栅22，形成与浮栅22接触的第二绝缘层26，形成 在第二绝缘层26上方的控制栅极28，在半导体层10中形成源极区域14和漏极区域16，在半导体层10上方沉积绝缘层40，并蚀刻绝缘层40以形成侧壁绝缘层 其中绝缘层40的蚀刻被导通，使得绝缘层40保持在浮动栅极40的上方，并且浮动栅极22不暴露。

公开(公告)号：US06355526B1

公开(公告)日：2002-03-12

申请号：US09272243

申请日：1999-03-19

申请人： Tomoyuki Furuhata

发明人： Tomoyuki Furuhata

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A non-volatile semiconductor memory device and a method of manufacturing that device. A silicon oxide layer is formed on a polysilicon layer. A control gate and a gate electrode are simultaneously formed by selectively etching the polysilicon layer by using the silicon oxide layer as a mask. A floating gate is then formed by selectively etching the polysilicon layer by using the silicon oxide layer on the control gate as a mask.

摘要翻译： 一种非易失性半导体存储器件及其制造方法。 在多晶硅层上形成氧化硅层。 通过使用氧化硅层作为掩模选择性地蚀刻多晶硅层，同时形成控制栅极和栅电极。 然后通过使用控制栅极上的氧化硅层作为掩模来选择性地蚀刻多晶硅层来形成浮栅。