公开(公告)号：US5973338A

公开(公告)日：1999-10-26

申请号：US947402

申请日：1997-10-08

申请人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

发明人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

IPC分类号： H01L29/68 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/1095 ,  H01L29/7395

摘要： An insulated gate type bipolar-transistor (IGBT) incorporates an excess voltage protecting function and drain voltage fixing function in a monolithic structure. Impurity concentration ND and the thickness of an n.sup.- type drain layer (3) is set so that a depletion region propagating from a p type base layer (7) reaches a p.sup.+ type drain layer at a voltage (V.sub.DSP) lower than a voltage (V.sub.DSS) at which avalanche breakdown is caused within the IGBT element when voltage is applied between the source and the drain.

摘要翻译： 绝缘栅型双极晶体管（IGBT）在整体结构中包含过电压保护功能和漏极电压固定功能。 杂质浓度ND和n型漏极层（3）的厚度被设定为使得从ap型基极层（7）传播的耗尽区域在低于电压（VDSS）的VDSP下达到p +型漏极层 ），当在源极和漏极之间施加电压时，在IGBT元件内引起雪崩击穿。

公开(公告)号：US5955750A

公开(公告)日：1999-09-21

申请号：US521158

申请日：1995-08-30

申请人： Stephen W. Byatt

发明人： Stephen W. Byatt

IPC分类号： H01L29/74 ,  H01L29/861 ,  H01L29/87 ,  H01L31/111

CPC分类号： H01L29/87

摘要： A four-region (PNPN) semiconductor device structure that provides greater flexibility in the setting of PN junction breakdown conditions. The four-region (PNPN) semiconductor device includes an additional N-type body at the junction between the inner N-type region and the inner P-type region, the additional N-type body including a first part adjacent to a second part, the first and second parts having different impurity concentrations from one another, both being of high impurity concentration than the inner N-type region and of lower impurity concentration than the inner P-type region.

摘要翻译： 一种四区域（PNPN）半导体器件结构，在PN结击穿条件的设置中提供更大的灵活性。 四区域（PNPN）半导体器件在内部N型区域和内部P型区域之间的连接处包括另外的N型体，附加N型体包括与第二部分相邻的第一部分， 第一和第二部分彼此具有不同的杂质浓度，两者的杂质浓度都高于内部N型区域，并且杂质浓度低于内部P型区域。

公开(公告)号：US5847416A

公开(公告)日：1998-12-08

申请号：US650996

申请日：1996-05-21

申请人： Kenji Ohta ,  Katumi Satoh

发明人： Kenji Ohta ,  Katumi Satoh

IPC分类号： H01L29/74 ,  G02B6/28 ,  G02B6/42 ,  H01L31/111 ,  H01L31/0232

CPC分类号： G02B6/4295 ,  G02B6/2808 ,  G02B6/421

摘要： A light travelling from a light transmission window (8) to a light receiving part (2) is transmitted first through a first light guide (11) of linear single core construction and next through a second light guide (12) which is bent and of multicore construction. Single core construction achieves a high light mixing effect, and accordingly the first light guide (11) makes a distribution of light intensity uniform. On the other hand, multicore construction has little light mixing effect, and raises little variation in distribution of incident light intensity. In other words, the second light guide (12) transmits the light to the light receiving part (2) without breaking the uniform distribution of light intensity achieved by the first light guide (11).

摘要翻译： 从光透射窗（8）向受光部（2）行进的光首先通过线状单芯结构的第一导光体（11）传播，接着穿过第二导光体（12） 多核建设。 单芯结构实现了高的光混合效果，因此第一光导（11）使光强均匀分布。 另一方面，多核构造具有很少的光混合效应，并且引起入射光强度分布的变化很小。 换句话说，第二光导（12）将光发射到光接收部（2）而不破坏由第一光导（11）实现的光强度的均匀分布。

公开(公告)号：US5831292A

公开(公告)日：1998-11-03

申请号：US637304

申请日：1996-04-24

申请人： Christopher Harris ,  Andrei Konstantinov ,  Erik Janzen

发明人： Christopher Harris ,  Andrei Konstantinov ,  Erik Janzen

IPC分类号： H01L29/24 ,  H01L29/423 ,  H01L29/739 ,  H01L29/74 ,  H01L31/0312 ,  H01L31/111

CPC分类号： H01L29/7395 ,  H01L29/42376 ,  H01L29/1608

摘要： A transistor of SiC having an insulated gate comprises a drain contact with a highly doped substrate layer formed on the drain. The substrate layer is of p-type or of n-type. For a p-type transistor, a highly doped n-type buffer layer may optionally be formed on top of the substrate layer. A low doped n-type drift layer, a highly doped p-type base layer, a highly doped n-type source region, and a source contact are then superimposed on the substrate layer. A vertical trench extends through the source region and the base layer to at least the drift layer. The trench has a wall next to these layers. A gate electrode extends vertically along the wall and at least over a vertical extension of the base layer. An insulating layer is arranged between the gate electrode and at least the base layer whereby an inversion channel is formed for electron transport from the source contact to the drain contact. An additional low doped p-type layer is arranged in the channel region laterally to the base layer, between the base layer and the insulating layer. The additional layer extends vertically over at least the base layer.

摘要翻译： 具有绝缘栅极的SiC晶体管包括与形成在漏极上的高掺杂衬底层的漏极接触。 衬底层是p型或n型。 对于p型晶体管，高可掺杂的n型缓冲层可任选地形成在衬底层的顶部上。 然后将低掺杂n型漂移层，高掺杂的p型基极层，高掺杂的n型源极区和源极接触叠加在衬底层上。 垂直沟槽延伸穿过源极区域和基极层至少到漂移层。 沟槽在这些层旁边有一个墙壁。 栅电极沿着壁垂直延伸，并且至少在基层的垂直延伸部上延伸。 绝缘层设置在栅极电极和至少基极层之间，由此形成用于从源极接触到漏极接触的电子传输的反转沟道。 在沟道区域中，在基底层和绝缘层之间的基底层侧向布置有附加的低掺杂p型层。 附加层至少在基层上垂直延伸。

公开(公告)号：US5828089A

公开(公告)日：1998-10-27

申请号：US641676

申请日：1996-05-01

申请人： Eric Bernier

发明人： Eric Bernier

IPC分类号： H01L29/74 ,  H01L27/02 ,  H01L29/747 ,  H02H9/04 ,  H04Q3/42 ,  H01L23/62 ,  H01L31/111

CPC分类号： H01L27/0248

摘要： A monolithic component for protecting a subscriber line interface circuit includes, in an N-type substrate, whose bottom surface is coated with a first uniform metallization, first and second portions separated by a P-type isolation wall. The first portion includes two vertical diodes having a common cathode corresponding to the bottom surface of the substrate, two vertical transistors having a common collector and a common base, the collectors corresponding to the bottom surface of the substrate. The second portion includes two sets each including a pair of head-to-tail parallel-connected vertical thyristors and a pair of head-to-tail parallel-connected vertical zener diodes for controlling the conduction of these thyristors.

摘要翻译： 用于保护用户线路接口电路的单片部件包括在其底表面被第一均匀金属化的N型衬底中，第一和第二部分被P型隔离壁隔开。 第一部分包括具有对应于衬底的底表面的公共阴极的两个垂直二极管，具有公共集电极和公共基底的两个垂直晶体管，所述集电极对应于衬底的底表面。 第二部分包括两组，每组包括一对头 - 尾并行连接的垂直晶闸管和一对头对称并联连接的垂直齐纳二极管，用于控制这些晶闸管的导通。

公开(公告)号：US5808344A

公开(公告)日：1998-09-15

申请号：US795714

申请日：1997-02-04

申请人： Khalid EzzEldin Ismail ,  Bernard S. Meyerson

发明人： Khalid EzzEldin Ismail ,  Bernard S. Meyerson

IPC分类号： H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/1054 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/7393 ,  H01L29/78

摘要： A dual transistor CMOS inverter can be built wherein a single gate is shared by two MOS transistors but only one transistor can be turned on at a time. A CMOS inverter function is provided. Further, a dual transistor logic function is described incorporating a combination of a lateral bipolar transistor (LBT) and a metal-oxide-semiconductor transistor (MOST). The gate of the MOST is used to turn on and off the base of the LBT. When the base is turned on, the LBT is turned on and off depending on the base voltage. This device has, thus, two inputs and can perform logic functions such as OR or NAND, which would typically require four transistors. The invention solves the problem of device density to perform logic by forming stacked devices with shared electrodes.

摘要翻译： 可以构建双晶体管CMOS反相器，其中单个栅极由两个MOS晶体管共享，但一次只能接通一个晶体管。 提供CMOS反相器功能。 此外，描述了结合横向双极晶体管（LBT）和金属氧化物半导体晶体管（MOST）的组合的双晶体管逻辑功能。 MOST的栅极用于打开和关闭LBT的基极。 当基座接通时，LBT根据基极电压打开和关闭。 因此，该器件具有两个输入并且可以执行诸如OR或NAND的逻辑功能，其通常将需要四个晶体管。 本发明通过形成具有共享电极的堆叠器件来解决器件密度的问题来执行逻辑。

公开(公告)号：US5808326A

公开(公告)日：1998-09-15

申请号：US843732

申请日：1997-04-21

申请人： Eric Bernier ,  Christian Ballon

发明人： Eric Bernier ,  Christian Ballon

IPC分类号： H01L29/866 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/08 ,  H02H3/22 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L27/0248 ,  H01L27/0814

摘要： A protection semiconductor component includes at least two pairs of main Shockley diodes, each pair including two parallel diodes, head-to-tail connected between a front surface metallization and a rear surface metallization, the rear surface metallization being common to the two pairs of diodes. Each of the main diodes whose blocking junction corresponds to a distinct well on the side of the front surface is associated with at least one auxiliary Shockley diode having the same polarity and a lower triggering threshold, the triggering of one auxiliary diode thus causing the triggering of the other auxiliary diode and of the associated main Shockley diodes.

摘要翻译： 保护半导体部件包括至少两对主Shockley二极管，每对包括两个并联二极管，前后连接在前表面金属化和后表面金属化之间，后表面金属化是两对二极管共同的 。 阻挡连接对应于前表面一侧的不同阱的每个主二极管与至少一个具有相同极性和较低触发阈值的辅助Shockley二极管相关联，因此触发一个辅助二极管，从而导致触发 另一个辅助二极管和相关的主Shockley二极管。

公开(公告)号：US5804841A

公开(公告)日：1998-09-08

申请号：US648819

申请日：1996-05-16

申请人： Katsumi Satoh ,  Kenji Ohta

发明人： Katsumi Satoh ,  Kenji Ohta

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L31/1113

摘要： An optical trigger thyristor having a light receiving portion 8 constructed of an n-type base layer front surface portion 5, a p-type semiconductor region 6, and a p-type front surface layer 7. The p-type front surface layer 7 is disposed so that it connects the front surfaces of the p-type semiconductor region 6 and a p-type base layer 3 and covers the exposed surface of the n-type base layer front surface portion 5. As a result, the n-type base layer front surface portion, which tends to be easily contaminated, is covered by the p-type front surface layer. Thus, contamination of the n-type base layer front surface is prevented. Consequently, the concentration of impurities in the front surface portion of the n-type base layer does not vary. Thus, there is high arc sensitivity without deterioration of the voltage blocking characteristic.

摘要翻译： 具有由n型基底层前表面部分5，p型半导体区域6和p型前表面层7构成的光接收部分8的光学触发晶闸管.p型正面层7是 被配置为连接p型半导体区域6的前表面和p型基底层3并且覆盖n型基底层前表面部分5的暴露表面。结果，n型基底 容易被污染的层前表面部分被p型前表面层覆盖。 因此，防止了n型基底层正面的污染。 因此，n型基底层的表面部分中的杂质浓度不变化。 因此，没有劣化电压阻挡特性的电弧敏感性高。

公开(公告)号：US5780877A

公开(公告)日：1998-07-14

申请号：US795624

申请日：1997-02-06

申请人： Bernd Bireckoven ,  Dirk Hoheisel ,  Ning Qu

发明人： Bernd Bireckoven ,  Dirk Hoheisel ,  Ning Qu

IPC分类号： H01L29/74 ,  F02P7/03 ,  H01L31/111

CPC分类号： F02P7/035 ,  H01L31/1113

摘要： A break-over photodiode, designed as a light-sensitive thyristor, can be stacked using a series connection with a plurality of break-over photodiodes, such stacking representing a high-voltage break-over diode. The break-over photodiode can be triggered by lateral illumination in an edge zone, and includes a gate-layer resistivity under the emitter which is greater in an edge zone of the break-over photodiode than in the central zone of the break-over photodiode. The light sensitivity of the laterally illuminatable break-over photodiode is increased by a greater gate-layer resistivity in the edge zone as compared to the central zone.

摘要翻译： 设计为感光晶闸管的断路光电二极管可以使用与多个断开光电二极管的串联连接堆叠，这样堆叠代表高压断路二极管。 断路光电二极管可以通过边缘区域中的横向照明来触发，并且在发射极之下包括栅极层电阻率，其在断开光电二极管的边缘区域比在断开光电二极管的中心区域更大 。 与中心区域相比，侧向可照明的断开光电二极管的光敏度在边缘区域中增加了更大的栅极层电阻率。

公开(公告)号：US5773852A

公开(公告)日：1998-06-30

申请号：US679564

申请日：1996-07-15

申请人： Min-Koo Han ,  Byeong-Hoon Lee ,  Moo-Sup Lim ,  Yearn-Ik Choi ,  Jung-Eon Park ,  Won-Oh Lee

发明人： Min-Koo Han ,  Byeong-Hoon Lee ,  Moo-Sup Lim ,  Yearn-Ik Choi ,  Jung-Eon Park ,  Won-Oh Lee

IPC分类号： H01L29/78 ,  H01L29/72 ,  H01L29/739 ,  H01L29/786 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7394

摘要： A shorted anode lateral insulated gate bipolar transistor includes a semiconductor layer of a first conductivity type, a first current electrode, a second current electrode, a first insulation layer, a first gate electrode, a second gate electrode, a first high concentration impurity region of a second conductivity type, a low concentration impurity region of the second conductivity type, a first high concentration impurity region of the first conductivity type, a second high concentration impurity region of the second conductivity type, a third high concentration impurity region of the second conductivity type, and a second high concentration impurity region of the first conductivity type.

摘要翻译： 短路阳极横向绝缘栅双极晶体管包括第一导电类型的半导体层，第一电流电极，第二电流电极，第一绝缘层，第一栅极电极，第二栅极电极，第一高浓度杂质区域 第二导电类型的低浓度杂质区，第二导电类型的第一高浓度杂质区，第二导电类型的第一高浓度杂质区，第二导电类型的第二高浓度杂质区，第二导电类型的第二高浓度杂质区， 型和第一导电类型的第二高浓度杂质区。