公开(公告)号：US11838398B2

公开(公告)日：2023-12-05

申请号：US18051138

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonju Lee ,  Jiyoung Kim ,  Jaehyun Park ,  Seuk Son ,  Sooeun Lee ,  Dongchul Choi

IPC: H04L7/033 ,  H03K3/037 ,  H03K5/26 ,  H03K5/00

CPC classification number: H04L7/033 ,  H03K3/037 ,  H03K5/26 ,  H03K2005/00286

Abstract: A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.

公开(公告)号：US20230384372A1

公开(公告)日：2023-11-30

申请号：US17872479

申请日：2022-07-25

Applicant: Changxin Memory Technologies, Inc.

Inventor： Zengquan WU

IPC: G01R31/317 ,  H03K3/037 ,  H03K5/01

CPC classification number: G01R31/31725 ,  H03K3/037 ,  H03K5/01 ,  H03K2005/00019

Abstract: A method for evaluating performance of a sequential logic element includes: inputting a preset clock signal and a data signal to a sequential logic element to be tested; decrementing a setup time of the sequential logic element from a first preset value to a second preset value based on a preset decrement step, where the first preset value is determined by a setup time when the sequential logic element to be tested outputs a target sampled value, and the second preset value is determined by a setup time when the sequential logic element outputs a reverse value of the target sampled value; and determining an evaluation parameter of the sequential logic element based on a sampled value output by the sequential logic element after each decrement of the setup time, and evaluating performance of the sequential logic element based on the evaluation parameter of the sequential logic element to be tested.

公开(公告)号：US20230378939A1

公开(公告)日：2023-11-23

申请号：US18362322

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

Inventor： XiuLi YANG ,  Kuan CHENG ,  He-Zhou WAN ,  Ching-Wei WU ,  Wenchao HAO

IPC: H03K3/012 ,  G11C7/10 ,  G11C7/22 ,  H03K3/037

CPC classification number: H03K3/012 ,  G11C7/10 ,  G11C7/222 ,  H03K3/0372

Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.

公开(公告)号：US11824539B2

公开(公告)日：2023-11-21

申请号：US17885386

申请日：2022-08-10

Applicant: Synopsys, Inc.

Inventor： Hardik Arora ,  Amit Verma ,  Basannagouda Somanath Reddy

IPC: H03K3/00 ,  H03K3/037 ,  G06F1/10 ,  H03K19/20 ,  H03K21/10

CPC classification number: H03K3/037 ,  G06F1/10 ,  H03K19/20 ,  H03K21/10

Abstract: Clock multiplexer circuitry outputs one of a first or second clock signal. First selection circuitry is connected in series with first counter circuitry. The first selection circuitry and the first counter circuitry receive a first clock signal and a first selection signal. A first control signal is generated based on the first clock signal and the first selection signal. Second selection circuitry is connected in series with second counter circuitry. The second selection circuitry and the second counter circuitry receive a second clock signal and a second selection signal. A second control signal is generated based on the second clock signal and the second selection signal. The output circuitry is connected to the first counter circuitry and the second counter circuitry. The output circuitry outputs one of the first clock signal and the second clock signal based on the first control signal and the second control signal.

公开(公告)号：US20230361768A1

公开(公告)日：2023-11-09

申请号：US18202372

申请日：2023-05-26

Applicant: Littelfuse, Inc.

Inventor： BRET R. HOWE

IPC: H03K17/13 ,  H03K19/20 ,  H03K3/037

CPC classification number: H03K17/13 ,  H03K19/20 ,  H03K3/037

Abstract: A relay circuit, including a solid state relay switch, connected to a first relay line and to a charging capacitor, and connected to a second relay line. The relay circuit may also include a solid state relay control circuit, coupled between the charging capacitor and the solid state relay switch. The solid state relay control circuit may include a voltage detection circuit, having an input coupled to an output of the charging capacitor, and having an output arranged to generate a LOW voltage signal when a voltage level of the charging capacitor is below a low threshold value. The solid state relay control circuit may also include a zero crossing circuit, coupled to the first relay line and the second relay line, and having an output to generate a clock signal when a zero crossing event takes place between the first relay line and the second relay line.

公开(公告)号：US20230358806A1

公开(公告)日：2023-11-09

申请号：US18354501

申请日：2023-07-18

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Marco CASARSA

IPC: G01R31/3177 ,  H03K3/037 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  H03K3/0372 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318594 ,  H03K19/21

Abstract: The disclosure relates to a scan chain circuit comprising cascaded flip-flops having a functional input node and a test input node configured to be selectively coupled to logic circuitry at a clock edge time. A clock line is provided configured to distribute one or more clock signals to the flip-flops in the chain, wherein the flip-flops in the chain have active clock edges applied thereto at respective clock edge times. The chain of flip-flops comprise a set of flip-flops configured to receive an edge inversion signal and to selectively invert their active clock edges in response to the edge inversion signal being asserted.

公开(公告)号：US11809989B2

公开(公告)日：2023-11-07

申请号：US16919375

申请日：2020-07-02

Applicant: NVIDIA Corporation

Inventor： William James Dally

IPC: G06N3/045 ,  G06N3/084 ,  G06N3/08 ,  H03K3/037 ,  H03K5/01 ,  G06N3/063 ,  G06N3/04 ,  G06F1/12 ,  H03K19/003 ,  H03K5/00

CPC classification number: G06N3/08 ,  G06F1/12 ,  G06N3/04 ,  G06N3/063 ,  H03K3/037 ,  H03K5/01 ,  H03K19/003 ,  H03K2005/00013

Abstract: When a signal glitches, logic receiving the signal may change in response, thereby charging and/or discharging nodes within the logic and dissipating power. Providing a glitch-free signal may reduce the number of times the nodes are charged and/or discharged, thereby reducing the power dissipation. A technique for eliminating glitches in a signal is to insert a storage element that samples the signal after it is done changing to produce a glitch-free output signal. The storage element is enabled by a “ready” signal having a delay that matches the delay of circuitry generating the signal. The technique prevents the output signal from changing until the final value of the signal is achieved. The output signal changes only once, typically reducing the number of times nodes in the logic receiving the signal are charged and/or discharged so that power dissipation is also reduced.

公开(公告)号：US20230352085A1

公开(公告)日：2023-11-02

申请号：US18344459

申请日：2023-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC Nanjing Company Limited ,  TSMC China Company Limited

Inventor： Xiu-Li YANG ,  Lu-Ping KONG ,  Kuan CHENG ,  He-Zhou WAN

IPC: G11C11/419 ,  H03K3/037 ,  G11C11/418

CPC classification number: G11C11/419 ,  H03K3/0377 ,  G11C11/418

Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.

公开(公告)号：US20230350453A1

公开(公告)日：2023-11-02

申请号：US17733662

申请日：2022-04-29

Applicant: SanDisk Technologies LLC

Inventor： SHIV HARIT MATHUR ,  Avinash Pandit

IPC: G06F1/10 ,  H03K19/20 ,  H03K3/037

CPC classification number: G06F1/10 ,  H03K19/20 ,  H03K3/037

Abstract: Systems and methods disclosed herein provide for an improved glitch-free clock multiplexer exhibiting noise insensitivity with reduced power consumption and reduced physical area on a chip. The embodiments disclosed herein operate without any need of a reference clock. Due to which, clock interchangeability is possible at any point of time. An example glitch-free clock multiplexing according to the embodiments disclosed herein utilize a plurality of clock path circuits, each corresponding to a clock. The clock path circuits are activated responsive to a system startup signal. Based on a clock selection, the embodiments herein deactivate clock path circuits for unselected clocks and, dependent on the deactivation of the unselected clock path circuits, activate clock path circuits of any selected clocks.

公开(公告)号：US20230344352A1

公开(公告)日：2023-10-26

申请号：US18307631

申请日：2023-04-26

Applicant: pSemi Corporation

Inventor： Gary Chunshien Wu

IPC: H02M3/158 ,  H02M1/08 ,  H03K3/037 ,  H02M1/00

CPC classification number: H02M3/1584 ,  H02M1/08 ,  H03K3/037 ,  H02M1/0045 ,  H02M3/07

Abstract: Circuits and methods for providing a “bootstrap” power supply for level-shifter/driver (LS/D) circuits in a FET-based power converter. In a first embodiment, linear regulators and a bootstrap capacitor provide a bootstrap power supply for level-shifter/driver circuits in each tier of a multi-level FET-based power converter. In a second embodiment, floating charge circuits and bootstrap capacitors provide an improved bootstrap power supply for level-shifter and driver circuits in each tier of a multi-level FET-based power converter. More particularly, a floating charge circuit configured to be coupled to an associated bootstrap capacitor includes a first sub-circuit configured to pre-charge the associated bootstrap capacitor when coupled and a second sub-circuit configured to transfer charge between the bootstrap capacitor and a bootstrap capacitor coupled to an adjacent floating charge circuit.