公开(公告)号：US11700012B2

公开(公告)日：2023-07-11

申请号：US17306421

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeongjoon Ko ,  Junhan Bae ,  Hanseok Kim ,  Byeonggyu Park ,  Jaehyun Park ,  Hobin Song ,  Sooeun Lee

IPC: H03M1/74 ,  H04B1/16 ,  H04L25/03 ,  H03M1/66 ,  H03M7/16

CPC classification number: H03M1/742 ,  H03M1/66 ,  H03M7/165 ,  H04B1/16

Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

公开(公告)号：US20240302432A1

公开(公告)日：2024-09-12

申请号：US18597499

申请日：2024-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hobin SONG ,  Juyun Lee ,  Jiyoung Kim ,  Jaehyun Park ,  Sooeun Lee ,  Insik Hwang

IPC: G01R31/3183 ,  G01R31/317 ,  G01R31/3187 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/081

CPC classification number: G01R31/318328 ,  G01R31/31724 ,  G01R31/3187 ,  H03K5/13 ,  H03L7/0807 ,  H03K2005/00052 ,  H03L7/0812

Abstract: A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.

公开(公告)号：US11221644B2

公开(公告)日：2022-01-11

申请号：US16413212

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooeun Lee ,  Byungsub Kim

IPC: G06F1/10 ,  H04L25/03 ,  G06F1/08

Abstract: A system for transceiving data based on a clock transition time is provided. A transmitting device included in the system includes at least one first transmitting circuit configured to transmit data via a wired channel by changing a clock transition time based on the data, wherein the at least one first transmitting circuit includes a skew controller configured to output a skew clock generated by controlling a duty ratio and a skew of an input clock, and a phase-difference modulator configured to output a transmission signal including information about the data generated by changing a transition time of the skew clock based on the data.

公开(公告)号：US11838398B2

公开(公告)日：2023-12-05

申请号：US18051138

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonju Lee ,  Jiyoung Kim ,  Jaehyun Park ,  Seuk Son ,  Sooeun Lee ,  Dongchul Choi

IPC: H04L7/033 ,  H03K3/037 ,  H03K5/26 ,  H03K5/00

CPC classification number: H04L7/033 ,  H03K3/037 ,  H03K5/26 ,  H03K2005/00286

Abstract: A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.

公开(公告)号：US20220149863A1

公开(公告)日：2022-05-12

申请号：US17306421

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeongjoon Ko ,  Junhan Bae ,  Hanseok Kim ,  Byeonggyu Park ,  Jaehyun Park ,  Hobin Song ,  Sooeun Lee

IPC: H03M1/74 ,  H04B1/16 ,  H04L25/03

Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

公开(公告)号：US20190354133A1

公开(公告)日：2019-11-21

申请号：US16413212

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooeun Lee ,  Byungsub Kim

IPC: G06F1/10 ,  G06F1/08 ,  H04L25/03

Abstract: A system for transceiving data based on a clock transition time is provided. A transmitting device included in the system includes at least one first transmitting circuit configured to transmit data via a wired channel by changing a clock transition time based on the data, wherein the at least one first transmitting circuit includes a skew controller configured to output a skew clock generated by controlling a duty ratio and a skew of an input clock, and a phase-difference modulator configured to output a transmission signal including information about the data generated by changing a transition time of the skew clock based on the data.