MEMS device with tiltable structure and improved control

    公开(公告)号:US12066621B2

    公开(公告)日:2024-08-20

    申请号:US17720506

    申请日:2022-04-14

    CPC classification number: G02B26/0858 H02N2/028 H02N2/062

    Abstract: A MEMS device includes a semiconductor body with a cavity and forming an anchor portion, a tiltable structure elastically suspended over the cavity, first and second support arms to support the tiltable structure, and first and second piezoelectric actuation structures biasable to deform mechanically, generating a rotation of the tiltable structure around a rotation axis. The piezoelectric actuation structures carry first and second piezoelectric displacement sensors. When the tiltable structure rotates around the rotation axis, the displacement sensors are subject to respective mechanical deformations and generate respective sensing signals in phase opposition to each other, indicative of the rotation of the tiltable structure. The sensing signals are configured to be acquired in a differential manner.

    Processing system, related integrated circuit, system and method

    公开(公告)号:US12056074B2

    公开(公告)日:2024-08-06

    申请号:US18116912

    申请日:2023-03-03

    CPC classification number: G06F13/385 G06F13/4291 H04L25/0262

    Abstract: A UART communication interface manages transmission/reception at a baud rate using a baud-rate detection circuit. An edge detector detects edges in a reception signal and resets a count value in a digital counter circuit indicating a time between two consecutive edges. In the absence of a detected edge, the digital counter circuit increases the count value. At a newly detected edge, a validation circuit verifies the count value by asserting a second control signal when the count value is smaller than a maximum, and otherwise de-asserting the second control signal. A register provides a threshold signal by storing the count value when the second control signal is asserted. The threshold signal stored by the register is updated when the time is in a permitted range corresponding to the duration of a single bit. The baud rate may be determined as a function of the threshold signal.

    Noise shaper variable quantizer
    4.
    发明授权

    公开(公告)号:US12003247B2

    公开(公告)日:2024-06-04

    申请号:US17846520

    申请日:2022-06-22

    CPC classification number: H03M1/0668 H03M1/0626 H03M1/0648 H03M3/492 H03M3/51

    Abstract: A signal processing circuit includes a filter generating a quantizer input signal from a noise shaping input signal and a quantizer output signal. A quantizer divides the quantizer input signal by a scaling factor to produce a noise shaping output signal and multiplies the noise shaping output signal by the scaling factor to produce the quantizer output signal. Receiver circuitry scales the quantizer output signal by a second scaling factor. A dynamic range optimization circuit compares a current value of the noise shaping input signal to a threshold value, lowers or raises the scaling factor in response to the comparison, and proportionally lowers or raises the scaling factor such that a ratio between the scaling factor and second scaling factor remains substantially constant.

    Semiconductor device and corresponding method

    公开(公告)号:US11990442B2

    公开(公告)日:2024-05-21

    申请号:US17537112

    申请日:2021-11-29

    Abstract: A semiconductor die is mounted at a die area of a ball grid array package that includes an array of electrically-conductive ball. A power channel conveys a power supply current to the semiconductor die. The power channel is formed by an electrically-conductive connection plane layers extending in a longitudinal direction between a distal end at a periphery of the package and a proximal end at the die area. A distribution of said electrically-conductive balls is made along the longitudinal direction. The electrically-conductive connection plane layer includes subsequent portions in the longitudinal direction between adjacent electrically-conductive balls of the distribution. Respective electrical resistance values of the subsequent portions monotonously decrease from the distal end to the proximal end. A uniform distribution of power supply current over the length of the power channel is thus facilitated.

    Method of manufacturing semiconductor devices and corresponding device

    公开(公告)号:US11901250B2

    公开(公告)日:2024-02-13

    申请号:US17411585

    申请日:2021-08-25

    CPC classification number: H01L23/3107 H01L21/561 H01L23/18 H01L23/49838

    Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pat gstern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.

    Driver circuit for switching converters

    公开(公告)号:US11888397B2

    公开(公告)日:2024-01-30

    申请号:US17531024

    申请日:2021-11-19

    CPC classification number: H02M3/158 H02M1/0009

    Abstract: A DC-DC switching converter includes power switches selectively coupling an output terminal with a first voltage or with a second voltage. A driver stage is coupled with the power switches for driving the power switches. A driver control stage is coupled with the driver stage for controlling the operation of the driver stage. An output current sensing circuit is coupled with the output terminal and with the driver control stage, and is configured to sense a sign of an output current delivered by the DC-DC switching converter at the output terminal and to generate control signals for the driver control stage. The driver control stage controls the operation of the driver stage according to states of the control signals received from the output current sensing circuit, for selectively delaying the activation of the power switches depending on the sensed sign of the output current.

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