公开(公告)号：US12230602B2

公开(公告)日：2025-02-18

申请号：US17811560

申请日：2022-07-08

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Ludovic Fallourd ,  Christophe Serre

IPC: H01L23/00 ,  H01L21/78

Abstract: A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.

公开(公告)号：US12009658B2

公开(公告)日：2024-06-11

申请号：US17661352

申请日：2022-04-29

Applicant: STMicroelectronics (Tours) SAS

Inventor： Jean-Michel Simonnet ,  David Jouve ,  Frédéric Lanois

IPC: H02H9/04 ,  H01L27/02 ,  H02H9/00

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H02H9/005

Abstract: The present disclosure relates to a transient voltage suppression device comprising a single crystal semiconductor substrate doped with a first conductivity type comprising first and second opposing surfaces, a semiconductor region doped with a second conductivity type opposite to the first conductivity type extending into the substrate from the first surface, a first electrically conductive electrode on the first side contacting the semiconductor region and a second electrically conductive electrode on the second side contacting the substrate, a first interface between the substrate and the semiconductor region forming the junction of a TVS diode and a second interface between the first electrically conductive electrode and the semiconductor region or between the substrate and the second electrically conductive electrode forming the junction of a Schottky diode.

公开(公告)号：US20240128311A1

公开(公告)日：2024-04-18

申请号：US18357898

申请日：2023-07-24

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01G4/33 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L28/91 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L28/92

Abstract: The present disclosure relates to a capacitor including a first conductive layer over which is formed a stack, comprising from the upper face of the first layer, a first electrode, a first dielectric layer, a second electrode, and a second conductive layer, the stack comprising a stair step within the second conductive layer, the second electrode, and a part of the thickness of the first dielectric layer, the stair step being filled with a second dielectric layer so that the sidewalls of the first electrode are aligned with respect to the sidewalls of the second dielectric layer.

公开(公告)号：US11955480B2

公开(公告)日：2024-04-09

申请号：US17741900

申请日：2022-05-11

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed Boufnichel

IPC: H01L27/08 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01L27/0629 ,  H01L28/87 ,  H01L28/90

Abstract: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.

公开(公告)号：US11830873B2

公开(公告)日：2023-11-28

申请号：US16583090

申请日：2019-09-25

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Arnaud Yvon

IPC: H01L27/08 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L27/0814 ,  H01L21/8252 ,  H01L27/0676 ,  H01L29/8611 ,  H01L29/872

Abstract: The present description concerns an electronic device comprising a stack of a Schottky diode and of a bipolar diode, connected in parallel by a first electrode located in a first cavity and a second electrode located in a second cavity.

公开(公告)号：US20230230906A1

公开(公告)日：2023-07-20

申请号：US18154638

申请日：2023-01-13

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Nicolas MODE ,  Ludovic FALLOURD ,  Laurent BARREAU

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49805 ,  H01L23/49838 ,  H01L23/293 ,  H01L23/3135 ,  H01L21/486 ,  H01L21/565

Abstract: The present disclosure concerns a method of manufacturing an electronic component and the obtained component, comprising a substrate, comprising the successive steps of: depositing a first layer of a first resin activated by abrasion to become electrically conductive, on a first surface of said substrate comprising at least one electric contact and, at least partially, on the lateral flanks of said substrate; partially abrading said first layer on the flanks of said substrate.

公开(公告)号：US11677236B2

公开(公告)日：2023-06-13

申请号：US17197719

申请日：2021-03-10

Applicant: STMicroelectronics (Tours) SAS

Inventor： Eric Colleoni

IPC: H02H9/04 ,  H02H3/087 ,  H02M1/088 ,  H02M1/32

CPC classification number: H02H9/045 ,  H02H3/087 ,  H02M1/088 ,  H02M1/32 ,  H02M1/322

Abstract: A device for discharging a capacitor includes a resistive component having a resistance value selectable from among at least three resistance values. The device is configured to be connected in parallel with the capacitor. A circuit operates to select the resistance value of the resistive component.

公开(公告)号：US20230074505A1

公开(公告)日：2023-03-09

申请号：US17903214

申请日：2022-09-06

Applicant: STMicroelectronics (Tours) SAS

Inventor： Yannick HAGUE ,  Romain LAUNOIS

IPC: H02M7/162 ,  H02M7/219 ,  H02M1/08

Abstract: A converter includes first and second transistors coupled between first and second nodes, and first and second thyristors coupled between the first and second nodes. The converter is controlled for operation to: in first periods, turn the first transistor and second thyristor on and turn the second transistor and the first thyristor off, and in second periods, turn the first transistor and the second thyristor off and turn the second transistor and the first thyristor on. Further control of converter operation includes, for a third period following each first period, turning the first and second transistors off, turning the second thyristor off, and injecting a current into the gate of the first thyristor. Additional control of converter operation includes, for a fourth period following each second period, turning the first and second transistors off, turning the first thyristor off, and injecting a current into the gate of the second thyristor.

公开(公告)号：US20230048614A1

公开(公告)日：2023-02-16

申请号：US17880473

申请日：2022-08-03

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Patrick HAUTTECOEUR

IPC: H01L21/324 ,  H01L21/02

Abstract: The present description concerns a method of manufacturing a device comprising at least one radio frequency component on a semiconductor substrate comprising: a) a laser anneal of a first thickness of the substrate on the upper surface side of the substrate; b) the forming of an insulating layer on the upper surface of the substrate; and c) the forming of said at least one radio frequency component on the insulating layer.

公开(公告)号：US11581304B2

公开(公告)日：2023-02-14

申请号：US16987066

申请日：2020-08-06

Applicant: STMicroelectronics (Tours) SAS

Inventor： Olivier Ory

IPC: H01L27/02 ,  H01L29/06

Abstract: The present disclosure provides an electronic device that includes a substrate. The substrate includes a well and a peripheral insulating wall laterally surrounding the well. At least one lateral bipolar transistor is formed in the well, and the at least one transistor has a base region extending under parallel collector and emitter regions. The peripheral insulating wall is widened in a first direction, parallel to the collector and emitter regions, so that the base region penetrates into the peripheral insulating wall.