公开(公告)号：US11942563B1

公开(公告)日：2024-03-26

申请号：US18327875

申请日：2023-06-01

申请人： XINTEC INC.

发明人： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

IPC分类号： H01L31/0352 ,  H01L31/02

CPC分类号： H01L31/03529 ,  H01L31/02005

摘要： A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

公开(公告)号：US11873212B2

公开(公告)日：2024-01-16

申请号：US17184443

申请日：2021-02-24

申请人： XINTEC INC.

发明人： Wei-Luen Suen ,  Jiun-Yen Lai ,  Hsing-Lung Shen ,  Tsang-Yu Liu

IPC分类号： B81C1/00 ,  B81B7/00

CPC分类号： B81B7/0067 ,  B81C1/00317 ,  B81B2203/0353 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0194

摘要： A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

公开(公告)号：US20230280231A1

公开(公告)日：2023-09-07

申请号：US18175416

申请日：2023-02-27

申请人： XINTEC INC.

发明人： Jui Yi KUO ,  Chung Yu LI ,  Yi Fan HU

IPC分类号： G01M3/04

CPC分类号： G01M3/04

摘要： A leakage detecting assembly includes a sheet leakage detecting module, a signal output unit, and a monitoring control system. The sheet leakage detecting module covers a wielding area or a connection area of a pipeline, and surrounds the pipeline. The sheet leakage detecting module is in direct contact with an outer surface of the pipeline. The signal output unit is electrically connected to the sheet leakage detecting module. The monitoring control system is electrically connected to the signal output unit.

公开(公告)号：US11476293B2

公开(公告)日：2022-10-18

申请号：US16950810

申请日：2020-11-17

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Tsang-Yu Liu ,  Po-Han Lee

IPC分类号： H01L27/146 ,  H01L23/00

摘要： A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

公开(公告)号：US11450697B2

公开(公告)日：2022-09-20

申请号：US16581594

申请日：2019-09-24

申请人： XINTEC INC.

发明人： Kuei-Wei Chen ,  Chia-Ming Cheng ,  Chia-Sheng Lin

IPC分类号： H01L27/146

摘要： A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

公开(公告)号：US20220216131A1

公开(公告)日：2022-07-07

申请号：US17560196

申请日：2021-12-22

申请人： XINTEC INC.

发明人： Po-Han LEE ,  Wei-Ming CHIEN

IPC分类号： H01L23/48 ,  H01L29/20 ,  H01L23/498

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second surface opposite thereto. A gallium nitride (GaN)-based device layer is formed on the first surface of the semiconductor substrate and has source, drain, and gate contact regions. First, second, and third through-substrate vias (TSVs) pass through the semiconductor substrate and are respectively electrically connected to the source, drain, and gate contact regions. An insulating liner layer is formed on the second surface of the semiconductor substrate and extends into the semiconductor substrate to separate the second and third TSVs from the semiconductor substrate. A semiconductor package assembly including the semiconductor device structure is also provided.

公开(公告)号：US20210343591A1

公开(公告)日：2021-11-04

申请号：US17373773

申请日：2021-07-13

申请人： XINTEC INC.

发明人： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L21/02

摘要： A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

公开(公告)号：US11121031B2

公开(公告)日：2021-09-14

申请号：US16668570

申请日：2019-10-30

申请人： XINTEC INC.

发明人： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L21/02

摘要： A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

公开(公告)号：US20210210436A1

公开(公告)日：2021-07-08

申请号：US17140964

申请日：2021-01-04

申请人： XINTEC INC.

发明人： Chia-Ming CHENG ,  Shu-Ming CHANG

IPC分类号： H01L23/552 ,  H01L23/528 ,  H01L23/66

摘要： A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

公开(公告)号：US11038077B2

公开(公告)日：2021-06-15

申请号：US16291637

申请日：2019-03-04

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Po-Han Lee ,  Chien-Min Lin ,  Yi-Rong Ho

IPC分类号： H01L31/12 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0216 ,  H01L31/18 ,  H01L31/028

摘要： A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.