公开(公告)号：US09947716B2

公开(公告)日：2018-04-17

申请号：US15358852

申请日：2016-11-22

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Hsiao-Lan Yeh ,  Chia-Sheng Lin ,  Yi-Ming Chang ,  Po-Han Lee ,  Hui-Hsien Wu ,  Jyun-Liang Wu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chien-Min Lin

IPC分类号： H01L27/146 ,  H01L21/48 ,  H01L21/67 ,  H01L23/18

CPC分类号： H01L27/14698 ,  H01L21/4803 ,  H01L21/67017 ,  H01L21/67132 ,  H01L23/18 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687

摘要： A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.

公开(公告)号：US09613904B2

公开(公告)日：2017-04-04

申请号：US15140289

申请日：2016-04-27

申请人： XINTEC INC.

发明人： Yu-Tung Chen ,  Chien-Min Lin ,  Chuan-Jin Shiu ,  Chih-Wei Ho ,  Yen-Shih Ho

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L23/04 ,  H01L23/52 ,  H01L23/528 ,  H01L21/027 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/5283 ,  H01L21/0271 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/0557

摘要： A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a conductive pad. The second substrate has a through via, a sidewall surface surrounding the through via, a first surface, and a second surface opposite to the first surface. The through via penetrates through the first and second surfaces. The conductive pad is aligned with the through via. The dam layer is located between the first substrate and the second surface. The dam layer protrudes toward the through via. The photoresist layer is located on the first surface, the sidewall surface, the dam layer protruding toward the through via, and between the conductive pad and the dam layer protruding toward the through via. The conductive layer is located on the photoresist layer and the conductive pad.

公开(公告)号：US11038077B2

公开(公告)日：2021-06-15

申请号：US16291637

申请日：2019-03-04

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Po-Han Lee ,  Chien-Min Lin ,  Yi-Rong Ho

IPC分类号： H01L31/12 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0216 ,  H01L31/18 ,  H01L31/028

摘要： A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.

公开(公告)号：US09403672B2

公开(公告)日：2016-08-02

申请号：US14819174

申请日：2015-08-05

申请人： XINTEC INC.

发明人： Chien-Min Lin

IPC分类号： B81B7/00 ,  H01L21/48 ,  B81C1/00 ,  H01L23/498

CPC分类号： B81B7/007 ,  B81B7/0058 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2207/096 ,  B81C1/00301 ,  B81C1/00682 ,  B81C2203/0118 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes forming a bump on a lower surface of an interposer. A first insulation layer is formed to cover the lower surface and bump. A trench is formed extending from the lower towards an upper surface of the interposer. A polymer supporting adhesive layer is formed to surround the bump and couples between the interposer and a semiconductor chip. The semiconductor chip has at least a sensing component and a conductive pad electrically connected to the sensing component, and the bump is connected to the conductive pad. A via is formed extending from the upper towards the lower surface. A second insulation layer is formed to cover the upper surface and the via. A redistribution layer is formed on the second insulation layer and in the via. A packaging layer is formed to cover the redistribution layer and has a second opening.

摘要翻译： 一种方法包括在插入器的下表面上形成凸块。 形成第一绝缘层以覆盖下表面和凸起。 形成从插入件的下表面延伸到上表面的沟槽。 形成聚合物支持粘合剂层以围绕凸起并且在插入器和半导体芯片之间耦合。 半导体芯片具有至少一个感测部件和电连接到感测部件的导电焊盘，并且凸块连接到导电焊盘。 通孔形成为从上部向下表面延伸。 形成第二绝缘层以覆盖上表面和通孔。 在第二绝缘层和通孔中形成再分布层。 形成包装层以覆盖再分布层并具有第二开口。

公开(公告)号：US09334156B2

公开(公告)日：2016-05-10

申请号：US14747507

申请日：2015-06-23

申请人： XINTEC INC.

发明人： Chien-Min Lin ,  Yu-Ting Huang ,  Chen-Ning Fu ,  Yen-Shih Ho

IPC分类号： B81B7/00 ,  B81C1/00 ,  H01L21/48 ,  H01L23/498

CPC分类号： B81B7/007 ,  B81C1/00182 ,  B81C1/00269 ,  B81C2201/0197 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.

摘要翻译： 芯片封装包括半导体芯片，插入件，聚合物粘合剂支撑层，再分布层和包装层。 半导体芯片具有传感器装置和与感测装置电连接的导电焊盘，并且插入器设置在半导体芯片上。 插入器具有沟槽和通孔，沟槽暴露感测装置的一部分，并且通孔暴露导电垫。 聚合物粘合剂支撑层插入在半导体芯片和插入件之间，并且再分配层设置在插入件上和通孔中以与导电焊盘电连接。 包装层覆盖插入件和再分配层，其中封装层具有露出沟槽的开口。