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1.发明授权Semiconductor devices having tensile and/or compressive stress and methods of manufacturing 有权具有拉伸和/或压缩应力的半导体器件和制造方法公开(公告)号：US09368410B2
公开(公告)日：2016-06-14
申请号：US12033280
申请日：2008-02-19
IPC分类号： H01L29/78 , H01L21/762 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76205 , H01L21/823878 , H01L29/7846
摘要： A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.
摘要翻译： 公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。 该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。 该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。 第一氧化沟槽在通道中产生应变分量以增加器件性能。
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公开(公告)号：US08617412B2
公开(公告)日：2013-12-31
申请号：US12966370
申请日：2010-12-13
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译： 本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。 纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。 纳米线结构可以包括多个垂直堆叠的水平纳米线。
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3.发明申请CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD 审中-公开用于修改半导体器件中的应力的接触棒及相关方法公开(公告)号：US20130240997A1
公开(公告)日：2013-09-19
申请号：US13424319
申请日：2012-03-19
IPC分类号： H01L27/11 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823871 , H01L27/1104 , H01L29/7843
摘要： Solutions for forming stress optimizing contact bars and contacts are disclosed. In one aspect, a semiconductor device is disclosed including an n-type field effect transistor (NFET) having source/drain regions; a p-type field effect transistor (PFET) having source/drain regions; a stress inducing layer over both the NFET and the PFET, the stress inducing layer inducing only one of a compressive stress and a tensile stress; a contact bar extending through the stress inducing layer and coupled to at least one of the source/drain regions of a selected device of the PFET and the NFET to modify a stress induced in the selected device compared to a stress induced in the other device; and a round contact extending through the stress inducing layer and coupled to at least one of the source/drain regions of the other device of the PFET and the NFET.
摘要翻译： 公开了用于形成应力优化接触棒和触点的解决方案。 一方面，公开了一种具有源极/漏极区域的n型场效应晶体管（NFET）的半导体器件; 具有源极/漏极区域的p型场效应晶体管（PFET） 在NFET和PFET两者上的应力诱导层，应力诱导层仅引起压缩应力和拉伸应力之一; 接触棒延伸穿过应力感应层并且耦合到PFET和NFET的所选器件的源/漏区中的至少一个，以修改与在另一器件中感应的应力相比在所选器件中感应的应力; 以及延伸穿过应力感应层并且耦合到PFET和NFET的另一个器件的源极/漏极区域中的至少一个的圆形接触。
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4.发明授权Damascene metal gate and shield structure, methods of manufacture and design structures 有权大马士革金属门和屏蔽结构，制造和设计结构的方法公开(公告)号：US08492214B2
公开(公告)日：2013-07-23
申请号：US13051510
申请日：2011-03-18
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L21/338
CPC分类号： H01L31/0232 , G06F17/5045 , G06F17/5054 , H01L27/14632 , H01L27/14683 , H01L29/66545
摘要： Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.
摘要翻译： 提供了具有镶嵌金属栅极和像素传感器单元屏蔽的半导体结构，制造方法和设计结构。 该方法包括在虚拟栅极结构上形成介电层。 该方法还包括在电介质层中形成一个或多个凹槽。 该方法还包括去除电介质层中的虚拟栅极结构以形成沟槽。 该方法还包括在沟槽中形成金属和在电介质层中形成多个凹槽以在沟槽中形成镶嵌金属栅极结构以及在一个或多个凹槽中形成一个或多个金属部件。
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5.发明申请公开(公告)号：US20120208329A1
公开(公告)日：2012-08-16
申请号：US13455176
申请日：2012-04-25
申请人： Andres Bryant , Edward J. Nowak
发明人： Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/84 , H01L21/8234
CPC分类号： H01L21/845 , H01L21/84 , H01L27/1203 , H01L27/1211
摘要： Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.
摘要翻译： 公开了具有集成电压均衡的具有串联的平面或非平面场效应晶体管（FET）的集成电路器件和形成器件的方法。 串联连接的FET包括沿着半导体本体定位的门，以限定用于串联连接的FET的沟道区。 源极/漏极区域位于沟道区域的相对侧上的半导体本体内，使得相邻栅极之间的半导体本体的每个部分包括用于一个场效应晶体管的一个源极/漏极区域，用于与另一个场效应晶体管的另一个源极/漏极区域相邻接 。 集成电压均衡通过具有期望电阻的并行导电层实现，并且位于串联连接的FET上，使得其与栅极电隔离，但与半导体本体内的源极/漏极区域接触。
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6.发明授权公开(公告)号：US08232627B2
公开(公告)日：2012-07-31
申请号：US12563195
申请日：2009-09-21
申请人： Andres Bryant , Edward J. Nowak
发明人： Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/06
CPC分类号： H01L21/845 , H01L21/84 , H01L27/1203 , H01L27/1211
摘要： Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.
摘要翻译： 公开了具有集成电压均衡的具有串联的平面或非平面场效应晶体管（FET）的集成电路器件和形成器件的方法。 串联连接的FET包括沿着半导体本体定位的门，以限定用于串联连接的FET的沟道区。 源极/漏极区域位于沟道区域的相对侧上的半导体本体内，使得相邻栅极之间的半导体本体的每个部分包括用于一个场效应晶体管的一个源极/漏极区域，用于与另一个场效应晶体管的另一个源极/漏极区域相邻接 。 集成电压均衡通过具有期望电阻的并行导电层实现，并且位于串联连接的FET上，使得其与栅极电隔离，但与半导体本体内的源极/漏极区域接触。
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公开(公告)号：US20120181588A1
公开(公告)日：2012-07-19
申请号：US13005650
申请日：2011-01-13
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L31/113 , G06F17/50 , H01L31/18
CPC分类号： H01L27/14614 , H01L27/14689
摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage.
摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元中的晶体管具有包括具有厚区域和薄区域的栅极电介质的栅极结构。 栅极结构的栅电极形成在栅极电介质的厚区域和栅极电介质的薄区域上。 栅极电介质的厚区域和栅极电介质的薄区为晶体管提供非对称阈值电压。
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公开(公告)号：US20120168873A1
公开(公告)日：2012-07-05
申请号：US12984773
申请日：2011-01-05
IPC分类号： H01L21/70 , G06F17/50 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/26586 , H01L21/823807 , H01L29/66659
摘要： Transmission gates, methods of fabricating transmission gates, and design structures for a transmission gate. The transmission gate includes an n-channel field effect transistor characterized by terminals that are asymmetrically doped and a p-channel field effect transistor characterized by terminals that are asymmetrically doped.
摘要翻译： 传输门，制造传输门的方法和传输门的设计结构。 传输门包括n沟道场效应晶体管，其特征在于不对称掺杂的端子和由不对称掺杂的端子表征的p沟道场效应晶体管。
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公开(公告)号：US20110193163A1
公开(公告)日：2011-08-11
申请号：US12702684
申请日：2010-02-09
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： A field effect device includes a channel region disposed on a silicon on insulator (SOI) layer, a gate portion disposed on the channel region, a source region disposed on the SOI layer and connected to the channel region having a horizontal surface and a vertical surface, the vertical surface arranged perpendicular to a linear axis of the device, a silicide portion that includes the horizontal surface and vertical surface of the source region, a contact including a metallic material in contact with the horizontal surface and vertical surface of the source region, and a drain region connected to the channel region disposed on the SOI layer.
摘要翻译： 场效应器件包括设置在绝缘体上硅（SOI）层上的沟道区域，设置在沟道区上的栅极部分，设置在SOI层上的源极区域，并连接到具有水平表面和垂直表面的沟道区域 垂直于装置的线性轴排列的垂直表面，包括源区域的水平表面和垂直表面的硅化物部分，包括与源区域的水平表面和垂直表面接触的金属材料的触点， 以及连接到设置在SOI层上的沟道区的漏极区。
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公开(公告)号：US07829407B2
公开(公告)日：2010-11-09
申请号：US11561488
申请日：2006-11-20
IPC分类号： H01L21/336 , H01L21/84 , H01L29/78
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
摘要翻译： 一种包括半导体材料的半导体器件，该半导体材料具有形成在该弯曲处的弯曲部和沟槽特征，以及至少部分地设置在沟槽特征中的栅极结构。 一种制造半导体结构的方法，包括在层上形成具有沟槽特征的半导体材料，在沟槽特征中至少部分地形成栅极结构，以及弯曲半导体材料，使得在反转沟道中的半导体材料中产生应力 栅结构的区域。
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