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1.
公开(公告)号:US20220240829A1
公开(公告)日:2022-08-04
申请号:US17584076
申请日:2022-01-25
IPC分类号: A61B5/30 , A61B5/00 , A61B5/0245 , A61B5/318 , A61B5/308
摘要: Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.
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公开(公告)号:US11265031B2
公开(公告)日:2022-03-01
申请号:US17091357
申请日:2020-11-06
摘要: Systems, methods, and computer program product embodiments are disclosed for removing any fixed frequency interfering signal from an input signal without introducing artifacts that are not part of the original signal of interest. An embodiment operates by using a virtual buffer with a length that matches a length of one cycle of an interfering signal. The embodiment extracts the interfering signal into the virtual buffer. For a sample in the next cycle of the interfering signal that corresponds to a virtual memory location for the virtual buffer, the embodiment can update one or more physical memory locations of the virtual buffer that are in the vicinity of the virtual memory location. This use of virtual buffer can remove any interfering signal without creating the artifacts associated with conventional notch filters.
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公开(公告)号:US11229391B2
公开(公告)日:2022-01-25
申请号:US17130842
申请日:2020-12-22
IPC分类号: A61B5/30 , A61B5/00 , A61B5/0245 , A61B5/318 , A61B5/308 , H04L12/26 , H04L12/863 , G16H40/63 , A61B18/00 , H02H9/04 , H03F3/45 , H03F3/68 , H03K5/125 , A61B5/0215 , A61B5/024 , A61B5/0538 , A61B18/14 , A61B5/361 , A61B5/363 , A61B5/352 , A61B5/366
摘要: Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.
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公开(公告)号:US10924424B2
公开(公告)日:2021-02-16
申请号:US16447275
申请日:2019-06-20
IPC分类号: H04L12/863 , H04L12/26 , A61B5/00 , A61B5/0402 , G16H40/63 , A61B5/0428 , H03F3/45 , H03K5/125 , A61B5/0215 , A61B5/0245 , A61B5/046 , A61B5/0464 , A61B18/14 , H03H17/02 , A61B18/00 , H02H9/04 , H03F3/68 , A61B5/024 , A61B5/0456 , A61B5/0472 , A61B5/0538
摘要: Systems, methods, and computer program product embodiments are disclosed for processing and displaying multiple signals in near real-time. An embodiment operates by processing, using a first digital signal processor (DSP) of a first signal module, a first packet associated with a first signal. The embodiment also processes, using a second DSP of a second signal module, a second packet associated with a second signal. The embodiment equalizes a first processing delay associated with the first DSP with a second processing delay associated with the second DSP such that the first DSP completes processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet. The embodiment then displays the processed first packet approximately simultaneously with the display of the processed second packet.
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5.
公开(公告)号:US20210029053A1
公开(公告)日:2021-01-28
申请号:US17065566
申请日:2020-10-08
IPC分类号: H04L12/863 , H04L12/26 , A61B5/00 , A61B5/0402 , G16H40/63 , A61B5/0428 , H03F3/45 , H03K5/125 , A61B5/0215 , A61B5/0245 , A61B5/046 , A61B5/0464 , A61B18/14
摘要: Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.
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公开(公告)号:US11896379B2
公开(公告)日:2024-02-13
申请号:US16543061
申请日:2019-08-16
发明人: Budimir S. Drakulic , Sina Fakhar , Thomas G. Foxall , Branislav Vlajinic , Samuel J. Asirvatham
IPC分类号: A61B5/0215 , A61B5/30 , A61B5/00 , A61B5/0245 , A61B5/318 , A61B5/308 , H04L43/02 , H04L47/50 , G16H40/63 , A61B18/00 , H02H9/04 , H03F3/45 , H03F3/68 , H03K5/125 , A61B5/024 , A61B5/0538 , A61B18/14 , A61B5/361 , A61B5/363 , A61B5/352 , A61B5/366
CPC分类号: A61B5/30 , A61B5/0245 , A61B5/308 , A61B5/318 , A61B5/7203 , A61B5/7225 , A61B5/7246 , A61B5/0006 , A61B5/0215 , A61B5/02405 , A61B5/0538 , A61B5/352 , A61B5/361 , A61B5/363 , A61B5/366 , A61B5/4836 , A61B5/7217 , A61B5/742 , A61B5/7435 , A61B18/1492 , A61B2018/00351 , A61B2018/00577 , A61B2562/18 , A61B2562/223 , G16H40/63 , H01L2924/14335 , H02H9/04 , H02H9/045 , H03F3/45 , H03F3/45475 , H03F3/68 , H03F2200/129 , H03F2200/171 , H03F2200/234 , H03F2200/375 , H03F2200/451 , H03F2203/45116 , H03F2203/45528 , H03F2203/45601 , H03K5/125 , H04L43/02 , H04L47/50 , H03H2017/0298 , H04B1/0014 , H04B1/0039
摘要: Systems, methods, and computer program product embodiments are disclosed for displaying cardiac signals based on a signal pattern. An embodiment operates by accessing an input cardiac signal. The embodiment matches a portion of the input cardiac signal to a known signal pattern. The embodiment then displays an indication of a degree of the match.
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7.
公开(公告)号:US20230240582A1
公开(公告)日:2023-08-03
申请号:US18115203
申请日:2023-02-28
IPC分类号: A61B5/30 , A61B5/00 , A61B5/0245 , A61B5/318 , A61B5/308
CPC分类号: A61B5/30 , A61B5/7203 , A61B5/7246 , A61B5/7225 , A61B5/0245 , A61B5/318 , A61B5/308 , H04L43/02
摘要: Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.
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8.
公开(公告)号:US11617530B2
公开(公告)日:2023-04-04
申请号:US17584076
申请日:2022-01-25
IPC分类号: A61B5/30 , A61B5/00 , A61B5/0245 , A61B5/318 , A61B5/308 , H04L43/02 , H04L47/50 , G16H40/63 , A61B18/00 , H02H9/04 , H03F3/45 , H03F3/68 , H03K5/125 , A61B5/0215 , A61B5/024 , A61B5/0538 , A61B18/14 , A61B5/361 , A61B5/363 , A61B5/352 , A61B5/366
摘要: Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.
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公开(公告)号:US20220249006A1
公开(公告)日:2022-08-11
申请号:US17719866
申请日:2022-04-13
发明人: Budimir S. DRAKULIC , Sina FAKHAR , Thomas G. FOXALL , Branislav VLAJINIC , Samuel J. ASIRVATHAM
IPC分类号: A61B5/30 , A61B5/00 , A61B5/0245 , A61B5/318 , A61B5/308
摘要: Systems, methods, and computer program product embodiments are disclosed for performing electrophysiology (EP) signal processing. An embodiment includes an electrocardiogram (ECG) circuit board configured to process an ECG signal. The embodiment further includes a plurality of intracardiac (IC) circuit boards, each configured to process a corresponding IC signal. The ECG circuit board and the plurality of IC circuit boards share substantially a same circuit configuration and components. The ECG circuit board further processes the ECG signal using substantially a same path as each IC circuit board uses to process its corresponding IC signal.
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公开(公告)号:US11324431B2
公开(公告)日:2022-05-10
申请号:US16582927
申请日:2019-09-25
发明人: Budimir S. Drakulic , Sina Fakhar , Thomas G. Foxall , Branislav Vlajinic , Samuel J. Asirvatham
IPC分类号: A61B5/0215 , A61B5/30 , A61B5/00 , A61B5/0245 , A61B5/318 , A61B5/308 , H04L43/02 , H04L47/50 , G16H40/63 , A61B18/00 , H02H9/04 , H03F3/45 , H03F3/68 , H03K5/125 , A61B5/024 , A61B5/0538 , A61B18/14 , A61B5/361 , A61B5/363 , A61B5/352 , A61B5/366
摘要: Systems, methods, and computer program product embodiments are disclosed for performing electrophysiology (EP) signal processing. An embodiment includes an electrocardiogram (ECG) circuit board configured to process an ECG signal. The embodiment further includes a plurality of intracardiac (IC) circuit boards, each configured to process a corresponding IC signal. The ECG circuit board and the plurality of IC circuit boards share substantially a same circuit configuration and components. The ECG circuit board further processes the ECG signal using substantially a same path as each IC circuit board uses to process its corresponding IC signal.
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