公开(公告)号：US08779554B2

公开(公告)日：2014-07-15

申请号：US13436322

申请日：2012-03-30

申请人： Georgios Vellianitis ,  Mark van Dal ,  Blandine Duriez

发明人： Georgios Vellianitis ,  Mark van Dal ,  Blandine Duriez

IPC分类号： H01L29/06 ,  H01L29/778

CPC分类号： H01L21/76264 ,  H01L21/30604 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7853

摘要： A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric.

摘要翻译： 一种器件包括半导体衬底和半导体衬底上的晶体管的沟道区域。 沟道区域包括半导体材料。 气隙设置在通道区域的下方并与之对准，通道区域的底表面暴露于气隙。 绝缘区域设置在气隙的相对侧上，其中沟道区域的底表面高于绝缘区域的顶表面。 晶体管的栅极电介质设置在沟道区的顶表面和侧壁上。 晶体管的栅电极在栅极电介质上方。

公开(公告)号：US20140061801A1

公开(公告)日：2014-03-06

申请号：US13600369

申请日：2012-08-31

申请人： Gerben Doornbos ,  Mark van Dal

发明人： Gerben Doornbos ,  Mark van Dal

IPC分类号： H01L27/12

CPC分类号： H01L27/0207 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/7843

摘要： The present disclosure describes a layout for stress optimization. The layout includes a substrate, at least two fin field effect transistors (FinFET) cells formed in the substrate, a FinFET fin designed to cross the two FinFET cells, a plurality of gates formed on the substrate, and an isolation unit formed between the first FinFET cell and the second FinFET cell. The two FinFET cells include a first FinFET cell and a second FinFET cell. The FinFET fin includes a positive charge FinFET (Fin PFET) fin and a negative charge FinFET (Fin NFET) fin. The isolation unit isolates the first FinFET cell from the second FinFET cell without breaking the FinFET fin.

摘要翻译： 本公开描述了用于应力优化的布局。 该布局包括衬底，在衬底中形成的至少两个鳍状场效应晶体管（FinFET）单元，设计成跨过两个FinFET单元的FinFET鳍，形成在衬底上的多个栅极，以及形成在第一 FinFET单元和第二个FinFET单元。 两个FinFET单元包括第一FinFET单元和第二FinFET单元。 FinFET鳍片包括正电荷FinFET（Fin PFET）鳍和负电荷FinFET（Fin NFET）鳍。 隔离单元将第一FinFET单元与第二FinFET单元隔离，而不会破坏FinFET鳍。

公开(公告)号：US20120319167A1

公开(公告)日：2012-12-20

申请号：US13162316

申请日：2011-06-16

申请人： Mark van Dal ,  Krishna Kumar Bhuwalka

发明人： Mark van Dal ,  Krishna Kumar Bhuwalka

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/66356 ,  H01L29/7391

摘要： A device includes a first source/drain region of a first conductivity type over a silicon substrate, wherein the first source/drain region is at a higher step of a two-step profile. The first source/drain region includes a germanium-containing region. A second source/drain region is of a second conductivity type opposite the first conductivity type, wherein the second source/drain region is at a lower step of the two-step profile. A gate dielectric includes a vertical portion in contact with a side edge the silicon substrate, and a horizontal portion in contact with a top surface of the silicon substrate at the lower step. The horizontal portion is connected to a lower end of the vertical portion. A gate electrode is directly over the horizontal portion, wherein a sidewall of the gate electrode is in contact with the vertical portion of the gate dielectric.

摘要翻译： 器件包括在硅衬底上的第一导电类型的第一源极/漏极区域，其中第一源极/漏极区域处于两阶段轮廓的较高台阶。 第一源极/漏极区域包括含锗区域。 第二源极/漏极区域具有与第一导电类型相反的第二导电类型，其中第二源极/漏极区域处于两阶段轮廓的较低台阶。 栅极电介质包括与硅衬底的侧边缘接触的垂直部分，以及在下部台阶处与硅衬底的顶表面接触的水平部分。 水平部分连接到垂直部分的下端。 栅电极直接在水平部分之上，其中栅电极的侧壁与栅电介质的垂直部分接触。

公开(公告)号：US08148052B2

公开(公告)日：2012-04-03

申请号：US12514777

申请日：2007-11-13

申请人： Anja Monique Vanleenhove ,  Peter Dirksen ,  David Van Steenwinckel ,  Gerben Doornbos ,  Casper Juffermans ,  Mark Van Dal

发明人： Anja Monique Vanleenhove ,  Peter Dirksen ,  David Van Steenwinckel ,  Gerben Doornbos ,  Casper Juffermans ,  Mark Van Dal

IPC分类号： G03F7/26

CPC分类号： G03F7/0035 ,  G03F7/11 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.

摘要翻译： 在衬底中或衬底上的至少一个器件层中形成图案的方法包括：用第一光致抗蚀剂层涂覆器件层; 使用第一掩模曝光第一光致抗蚀剂; 显影第一光致抗蚀剂层以在基底上形成第一图案; 用保护层涂覆基板; 处理保护层以在其中与第一光致抗蚀剂接触的地方发生变化，使得改变的保护层基本上不受随后的曝光和/或显影步骤的影响; 用第二光致抗蚀剂层涂覆基板; 使用第二掩模曝光所述第二光致抗蚀剂层; 并且显影所述第二光致抗蚀剂层以在所述基板上形成第二图案，而不会显着影响所述第一光致抗蚀剂层中的所述第一图案，其中所述第一和第二图案一起限定散布特征，其空间频率大于 第一和第二模式分开。 该方法在定义具有较小的特征尺寸的finFET器件的源极，漏极和鳍片特征方面具有特别的用途，而与主要的光刻工具不同。

公开(公告)号：US20090302389A1

公开(公告)日：2009-12-10

申请号：US12066707

申请日：2006-09-11

申请人： Robert Lander ,  Mark Van Dal ,  Jacob Hooker

发明人： Robert Lander ,  Mark Van Dal ,  Jacob Hooker

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28097 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/78

摘要： A method is described for forming gate structures with different metals on a single substrate. A thin semiconductor layer (26) is formed over gate dielectric (24) and patterned to be present in a first region (16) not a second region (18). Then, metal (30) is deposited and patterned to be present in the second region not the first. Then, a fully suicided gate process is carried out to result in a fully suicided gate structure in the first region and a gate structure in the second region including the fully suicided gate structure above the deposited metal (30).

摘要翻译： 描述了在单个衬底上形成具有不同金属的栅极结构的方法。 在栅极电介质（24）上形成薄的半导体层（26），并被图案化以存在于不是第二区域（18）的第一区域（16）中。 然后，金属（30）被沉积并图案化以存在于不是第一区域的第二区域中。 然后，进行完全自动的栅极处理，以在第一区域中产生完全自述的栅极结构，并且在第二区域中的栅极结构包括沉积金属（30）上方的完全自蚀的栅极结构。

公开(公告)号：US08722520B2

公开(公告)日：2014-05-13

申请号：US13298529

申请日：2011-11-17

申请人： Mark van Dal

发明人： Mark van Dal

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02639 ,  H01L21/02667 ,  H01L21/76229

摘要： A method is described what includes providing a substrate having a first trench and a second trench. An epitaxy material (crystalline material) is formed in the first trench and in the second trench. The top surface of the epitaxy material in the first trench is noncollinear with a top surface of the epitaxy material in the second trench. An amorphous semiconductor layer is formed on the crystalline material. Subsequently, the amorphous layer is converted, in part or in whole, into the crystalline semiconductor material. In an embodiment, a planarization process after the conversion provides crystalline regions having a coplanar top surface.

摘要翻译： 描述了包括提供具有第一沟槽和第二沟槽的衬底的方法。 在第一沟槽和第二沟槽中形成外延材料（晶体材料）。 第一沟槽中的外延材料的顶表面与第二沟槽中的外延材料的顶表面非共线。 在结晶材料上形成非晶半导体层。 随后，将非晶层部分或全部转变成晶体半导体材料。 在一个实施例中，转换后的平坦化处理提供了具有共面顶表面的结晶区域。

公开(公告)号：US20130256759A1

公开(公告)日：2013-10-03

申请号：US13431727

申请日：2012-03-27

申请人： Georgios Vellianitis ,  Mark van Dal ,  Blandine Duriez ,  Richard Oxland

发明人： Georgios Vellianitis ,  Mark van Dal ,  Blandine Duriez ,  Richard Oxland

IPC分类号： H01L29/12 ,  H01L21/20 ,  H01L27/088 ,  H01L29/02 ,  H01L29/165

CPC分类号： H01L29/41791 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.

公开(公告)号：US20120319211A1

公开(公告)日：2012-12-20

申请号：US13161649

申请日：2011-06-16

申请人： Mark van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Tsung-Lin Lee ,  Feng Yuan

发明人： Mark van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Tsung-Lin Lee ,  Feng Yuan

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

摘要： The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.

摘要翻译： 本公开提供了具有应变SiGe沟道的半导体器件和制造这种器件的方法。 在一个实施例中，半导体器件包括包括至少两个隔离特征的衬底，设置在至少两个隔离特征之间和之上的散热片衬底以及设置在散热片衬底的暴露部分之上的外延层。 根据一个方面，外延层可以设置在翅片衬底的顶表面和侧壁上。 根据另一方面，翅片基板可以基本上完​​全设置在至少两个隔离特征之上。

公开(公告)号：US20120088344A1

公开(公告)日：2012-04-12

申请号：US13298529

申请日：2011-11-17

申请人： Mark van Dal

发明人： Mark van Dal

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02639 ,  H01L21/02667 ,  H01L21/76229

摘要： A method is described what includes providing a substrate having a first trench and a second trench. An epitaxy material (crystalline material) is formed in the first trench and in the second trench. The top surface of the epitaxy material in the first trench is noncollinear with a top surface of the epitaxy material in the second trench. An amorphous semiconductor layer is formed on the crystalline material. Subsequently, the amorphous layer is converted, in part or in whole, into the crystalline semiconductor material. In an embodiment, a planarization process after the conversion provides crystalline regions having a coplanar top surface.

摘要翻译： 描述了包括提供具有第一沟槽和第二沟槽的衬底的方法。 在第一沟槽和第二沟槽中形成外延材料（晶体材料）。 第一沟槽中的外延材料的顶表面与第二沟槽中的外延材料的顶表面非共线。 在结晶材料上形成非晶半导体层。 随后，将非晶层部分或全部转变成晶体半导体材料。 在一个实施例中，转换后的平坦化处理提供了具有共面顶表面的结晶区域。

公开(公告)号：US20080258186A1

公开(公告)日：2008-10-23

申请号：US12158104

申请日：2006-12-12

申请人： Radu Surdeanu ,  Mark Van Dal

发明人： Radu Surdeanu ,  Mark Van Dal

IPC分类号： H01L29/00 ,  H01L21/8236

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2022 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/41775 ,  H01L29/66636 ,  H01L29/78654

摘要： A silicon on insulator device has a silicon layer (10) over a buried insulating layer (12). A nickel layer is deposited over a gate (16), on sidewall spacers (22) on the sides of the gate (16), and in a cavity on both sides of the gate (16) in the silicon layer (10). A doped amorphous silicon layer fills the cavity. Annealing then takes place which forms polysilicon (40) over the sidewall spacers (22) and gate (16), but where the nickel is adjacent to single crystal silicon (10) a layer of NiSi (44) migrates to the surface leaving doped single crystal silicon (42) behind, forming in one step a source, drain, and source and drain contacts.

摘要翻译： 硅绝缘体器件在掩埋绝缘层（12）上方具有硅层（10）。 镍层沉积在栅极（16）上，位于栅极（16）侧面上的侧壁间隔物（22）上，并沉积在硅层（10）中的栅极（16）两侧的空腔中。 掺杂的非晶硅层填充空腔。 然后发生在侧壁间隔物（22）和栅极（16）上形成多晶硅（40）的退火，但是当镍与单晶硅（10）相邻时，一层NiSi（44）迁移到表面，离开掺杂单 晶体硅（42）后面，形成一个源极，漏极以及源极和漏极触点。