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公开(公告)号：US20120314520A1
公开(公告)日：2012-12-13
申请号：US13589409
申请日：2012-08-20
CPC分类号： G11C11/4097 , G11C8/14 , G11C29/848 , G11C2207/002
摘要： A hierarchical memory architecture includes an array of memory sub-arrays, each of which includes an array of memory cells. Each sub-array is supported by local wordlines, local column-select lines, and bitlines. The local wordlines are controlled using main wordlines that extend past multiple sub-arrays in a direction parallel to a first axis, whereas the local column-select lines are controlled using main column-select lines that extend between sub-arrays in a direction perpendicular to the first axis. At the direction of signals presented on the local wordlines and column-select lines, subsets of the bitlines in each sub-array are connected to main data lines that extend over a plurality of the sub-arrays in parallel with the second axis. Some embodiments include redundant data resources that are selected based on a decoding of row addresses.
摘要翻译： 分层存储器架构包括存储器子阵列阵列，每个存储器子阵列包括存储器单元阵列。 每个子阵列由本地字线，本地列选择行和位线支持。 使用在与第一轴平行的方向延伸过多个子阵列的主要字线来控制本地字线，而使用主列选择线来控制本地列选择线，所述主列选择线在子阵列之间沿垂直于 第一轴。 在本地字线和列选择线上呈现的信号的方向上，每个子阵列中的位线的子集连接到与第二轴并行延伸在多个子阵列上的主数据线。 一些实施例包括基于行地址的解码来选择的冗余数据资源。
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公开(公告)号：US20120020161A1
公开(公告)日：2012-01-26
申请号：US13147474
申请日：2009-12-23
CPC分类号： G06F12/0246 , G06F2212/7209 , G11C16/10 , G11C16/32 , G11C16/3454 , G11C2216/22 , G11C2216/24
摘要： This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the overhead circuitry needed to control multiple concurrent operations may be reduced, thereby conserving valuable die space. Both the “program phase” and the “verify phase” of each state change operation cycle may be orchestrated across all planes at once, with shared timing and high voltage distribution.
摘要翻译： 本公开提供了一种多平面闪速存储器件，其中高电压编程（设置）或擦除（复位）脉冲被定时同时发生。 通过调节每个存储器平面（例如，具有其自己的专用阵列控制和页面缓冲器的存储器的每个逻辑或物理分区）施加高电压脉冲时，可以减少控制多个并发操作所需的开销电路，从而节省有价值的管芯空间。 每个状态改变操作周期的“程序阶段”和“验证阶段”可以在共享定时和高电压分配的情况下同时在所有平面上协调编组。
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公开(公告)号：US20110286280A1
公开(公告)日：2011-11-24
申请号：US13146521
申请日：2010-01-29
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a “rest period” between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译： 本公开提供了一种非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。 第一实施例使用脉冲位线控制，其中当需要改变相关联的存储器单元中的状态时，存储器单元通道和参考电压（响应于位线选择）之间的耦合是脉冲式的。 每个脉冲可以选择为小于约（20）纳秒，而脉冲之间的“休止期”通常被选择为约百纳秒或更大（例如，一微秒）的数量级。 由于使用位线控制，所以可以启用非常短的上升时间，能够产生（50）纳秒或更短的脉冲持续时间。 在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 如果需要，还可以使用分段字线或位线来最小化RC负载并且使足够短的上升时间使得脉冲变得坚固。
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公开(公告)号：US08645617B2
公开(公告)日：2014-02-04
申请号：US13126726
申请日：2009-10-15
IPC分类号： G06F12/00
CPC分类号： G11C16/26 , G11C16/10 , G11C2216/22
摘要： This disclosure provides a non-volatile memory device that concurrently processes multiple page reads, erases or writes involving the same memory space. The device relies upon a crossbar and a set of page buffers that may each be dynamically assigned to each read or write request. The device also separates memory array control from IO control, such that multiple cycle state change operations can be performed while the buffers are used to transfer data into and out of the buffers along an external data bus; using this structure, the memory device can accept multiple transactions where pages can be immediately loaded into buffers and then “pipelined” either for transfer to a write data register or to an external bus as appropriate. By significantly mitigating the substantial “busy time” associated with program and erase of non-volatile memory devices, especially flash devices, this disclosure greatly expands potential application of such devices.
摘要翻译： 本公开提供了一种非易失性存储器设备，其同时处理涉及相同存储器空间的多页读取，擦除或写入。 该设备依赖于交叉开关和一组页面缓冲器，每个页面缓冲区可以动态分配给每个读取或写入请求。 该器件还将存储器阵列控制与IO控制分离，使得可以执行多个周期状态改变操作，同时缓冲器用于沿着外部数据总线将数据传入和传出缓冲器; 使用这种结构，存储器件可以接受多个事务，其中页面可以被立即加载到缓冲器中，然后“流水线化”以适当地传送到写数据寄存器或外部总线。 通过显着减轻与非易失性存储器件，特别是闪存器件的编程和擦除相关的实质性“繁忙时间”，本发明大大扩展了这种器件的潜在应用。
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公开(公告)号：US08644078B2
公开(公告)日：2014-02-04
申请号：US13146521
申请日：2010-01-29
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译： 非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。 第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。 每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。 由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。 在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。
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公开(公告)号：US09570164B2
公开(公告)日：2017-02-14
申请号：US14240682
申请日：2012-08-10
CPC分类号： G11C13/0026 , G11C13/0002 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0088 , G11C2213/79
摘要： A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.
摘要翻译： 电阻RAM（RRAM）器件具有位线，字线，承载基本静态和非负电压的偏置电压的源极线，RRAM单元和耦合到位线电路的位线控制。 RRAM单元包括耦合到字线的栅极节点，耦合到源极线的偏置节点和耦合到位线的位线节点。 位线控制电路被配置为产生非负指令电压，以对RRAM单元执行相应的存储器操作。
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公开(公告)号：US08908454B2
公开(公告)日：2014-12-09
申请号：US13589409
申请日：2012-08-20
IPC分类号： G11C29/00 , G11C8/14 , G11C11/4097
CPC分类号： G11C11/4097 , G11C8/14 , G11C29/848 , G11C2207/002
摘要： A hierarchical memory architecture includes an array of memory sub-arrays, each of which includes an array of memory cells. Each sub-array is supported by local wordlines, local column-select lines, and bitlines. The local wordlines are controlled using main wordlines that extend past multiple sub-arrays in a direction parallel to a first axis, whereas the local column-select lines are controlled using main column-select lines that extend between sub-arrays in a direction perpendicular to the first axis. At the direction of signals presented on the local wordlines and column-select lines, subsets of the bitlines in each sub-array are connected to main data lines that extend over a plurality of the sub-arrays in parallel with the second axis. Some embodiments include redundant data resources that are selected based on a decoding of row addresses.
摘要翻译： 分层存储器架构包括存储器子阵列阵列，每个存储器子阵列包括存储器单元阵列。 每个子阵列由本地字线，本地列选择行和位线支持。 使用在与第一轴平行的方向延伸过多个子阵列的主要字线来控制本地字线，而使用主列选择线来控制本地列选择线，所述主列选择线在子阵列之间沿垂直于 第一轴。 在本地字线和列选择线上呈现的信号的方向上，每个子阵列中的位线的子集连接到与第二轴并行延伸在多个子阵列上的主数据线。 一些实施例包括基于行地址的解码来选择的冗余数据资源。
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公开(公告)号：US08908407B1
公开(公告)日：2014-12-09
申请号：US13548382
申请日：2012-07-13
CPC分类号： G11C15/046 , G11C15/02 , G11C15/04
摘要： A content addressable memory device based on an extremely compact design, potentially as small as 16F2 per memory cell. One embodiment is based on cells having two memory storage elements, such as RRAM elements. Each RRAM element and a respective FET are connected in series between a common matchline and a respective bitline. Cell content for each cell is matched against a bit of a search word by applying voltages to the respective bitlines dependent upon bit value and causing one of the two RRAM elements for each cell to discharge the matchline over a low resistance path in event of mismatch between the cell content and the bit. If no “quick” discharge occurs for multiple cells of a row, then a match is detected. In addition, a matchline recharge path to a high voltage bitline is substantially eliminated by controlling the FETs with specific wordline voltages.
摘要翻译： 基于非常紧凑的设计的内容可寻址存储器件，每个存储器单元可能小到16F2。 一个实施例基于具有两个存储器存储元件（诸如RRAM元件）的单元。 每个RRAM元件和相应的FET串联在公共匹配线和相应的位线之间。 每个单元的单元内容通过根据位值将电压施加到各个位线来匹配搜索字的位，并且使得每个单元的两个RRAM元件中的一个在低电阻路径上放电， 细胞内容和位。 如果对于一行的多个单元没有发生“快速”放电，则检测到匹配。 此外，通过用特定字线电压控制FET，基本上消除了对高电压位线的匹配线再充电路径。
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9.发明授权公开(公告)号：US08665642B2
公开(公告)日：2014-03-04
申请号：US13140345
申请日：2009-10-08
CPC分类号： G11C16/10 , G11C11/5628
摘要： A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits.
摘要翻译： 一种操作存储器件的方法包括接收要存储在器件中的多级单元中的第一组和第二组位。 从用于存储多级单元中的第一和第二位组的多个多级编码中选择多级编码。 每个多级编码包括用于相应多级单元的至少四个编码电平。 相应的多级编码具有与根据相应的多级编码将第一和第二组位编程到多级单元中相关联的成本。 基于相应编码的相应成本来选择多级编码。 第一和第二组位根据所选择的多级编码进行编码，以产生用于存储在设备中的编码数据，使得相应的多级单元存储来自第一和第二组位的相应位。
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公开(公告)号：US20130242640A1
公开(公告)日：2013-09-19
申请号：US13789557
申请日：2013-03-07
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/72 , G11C2213/79
摘要： A resistive change memory device includes a first conductive line, a second conductive line, and a resistive change memory cell that includes a resistive memory element coupled between the first conductive line and the second conductive line. The resistive change memory device also includes control circuitry to apply, via the first conductive line and the second conductive line, a first biasing condition to the resistive change memory cell for a reset operation and a second biasing condition to the resistive change memory cell for a restore operation. The restore operation is performed to counteract a decrease in resistance of the resistive memory element for a reset state of the resistive change memory cell. At least one of a voltage, current, and duration of the second biasing condition is greater than a corresponding voltage, current, or duration of the first biasing condition.
摘要翻译： 电阻变化存储器件包括第一导线，第二导线和电阻变化存储单元，其包括耦合在第一导线与第二导线之间的电阻性存储元件。 电阻变化存储器件还包括控制电路，用于经由第一导线和第二导线将第一偏置状态施加到电阻变化存储单元以进行复位操作，并将第二偏置状态施加到电阻变化存储器单元 恢复操作。 执行恢复操作以抵消电阻式存储单元在电阻变化存储单元的复位状态下的电阻降低。 第二偏置条件的电压，电流和持续时间中的至少一个大于第一偏置状态的对应的电压，电流或持续时间。
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