公开(公告)号：US09123589B2

公开(公告)日：2015-09-01

申请号：US13422686

申请日：2012-03-16

申请人： Min-Wook Park ,  Jong-In Kim ,  Jun-Ho Song ,  Bum-Ki Baek ,  Young-Soo Yoon

发明人： Min-Wook Park ,  Jong-In Kim ,  Jun-Ho Song ,  Bum-Ki Baek ,  Young-Soo Yoon

IPC分类号： G02F1/1333 ,  H01L33/08 ,  H01L27/12 ,  G02F1/1362

CPC分类号： H01L27/124 ,  G02F1/1362 ,  H01L27/1255

摘要： A display substrate includes a data line, a main gate line, and a first sub-pixel electrode formed on a base substrate. The display substrate further includes a first switching element connected to the data line. The display substrate further includes a second switching element connected to the data line, the main gate line, and a second sub-pixel electrode spaced apart from the first sub-pixel electrode. The display substrate further includes a third switching element connected to the data line and a secondary gate line adjacent to the main gate line. The display substrate further includes a shielding line spaced apart from the first and second sub-pixel electrodes, the shielding line overlapping the data line and receiving a reference voltage. The display substrate further includes an auxiliary electrode extending from the shielding line and overlapping an end electrode connected to the third switching element.

摘要翻译： 显示基板包括形成在基底基板上的数据线，主栅线和第一子像素电极。 显示基板还包括连接到数据线的第一开关元件。 显示基板还包括连接到数据线，主栅极线和与第一子像素电极间隔开的第二子像素电极的第二开关元件。 显示基板还包括连接到数据线的第三开关元件和与主栅极线相邻的次级栅极线。 显示基板还包括与第一和第二子像素电极间隔开的屏蔽线，屏蔽线与数据线重叠并接收参考电压。 显示基板还包括从屏蔽线延伸并与连接到第三开关元件的端电极重叠的辅助电极。

公开(公告)号：US08680527B2

公开(公告)日：2014-03-25

申请号：US12978446

申请日：2010-12-24

申请人： Yeon-Ju Kim ,  Sung-Jae Moon ,  Yun-Jung Cho ,  Bum-Ki Baek ,  Kwang-Hoon Lee ,  Byoung-Sun Na ,  Sung-Hoon Yang ,  Yoon-Jang Kim ,  Eun Cho

发明人： Yeon-Ju Kim ,  Sung-Jae Moon ,  Yun-Jung Cho ,  Bum-Ki Baek ,  Kwang-Hoon Lee ,  Byoung-Sun Na ,  Sung-Hoon Yang ,  Yoon-Jang Kim ,  Eun Cho

IPC分类号： H01L29/417

CPC分类号： G03F1/38 ,  G03F1/00 ,  G03F1/14 ,  G03F1/36 ,  H01L29/41733

摘要： A photomask includes; a source electrode pattern including; a first electrode portion which extends in a first direction, a second electrode portion which extends in the first direction and is substantially parallel to the first electrode portion, and a third electrode portion which extends from a first end of the first electrode portion to a first end of the second electrode portion and is rounded with a first curvature, a drain electrode pattern which extends in the first direction and is disposed between the first electrode portion and the second electrode portion, wherein an end of the drain electrode pattern is rounded to correspond to the third electrode portion; and a channel region pattern which is disposed between the source electrode pattern and the drain electrode pattern, wherein a center location of the first curvature and a center location of the rounded portion of the end of the drain electrode pattern are the same.

摘要翻译： 光掩模包括; 源电极图案，包括： 沿第一方向延伸的第一电极部分，沿第一方向延伸并基本上平行于第一电极部分的第二电极部分，以及从第一电极部分的第一端延伸到第一电极部分的第三电极部分， 并且以第一曲率圆形化，漏电极图案，其沿第一方向延伸并且设置在第一电极部分和第二电极部分之间，其中漏极电极图案的端部被圆化以对应 到所述第三电极部分; 以及设置在源极电极图案和漏极电极图案之间的沟道区域图案，其中第一曲率的中心位置和漏极电极图案的端部的圆形部分的中心位置相同。

公开(公告)号：US20130093658A1

公开(公告)日：2013-04-18

申请号：US13517872

申请日：2012-06-14

申请人： Jae Hwa PARK ,  Yeo Geon YOON ,  Jang-Il KIM ,  Kyung Ho KIM ,  Jong-In KIM ,  Min-Wook PARK ,  Bum Ki BAEK ,  Joon-Chul GOH ,  Young-Soo YOON ,  Hak Bum CHOI ,  Hyo-Seop KIM

发明人： Jae Hwa PARK ,  Yeo Geon YOON ,  Jang-Il KIM ,  Kyung Ho KIM ,  Jong-In KIM ,  Min-Wook PARK ,  Bum Ki BAEK ,  Joon-Chul GOH ,  Young-Soo YOON ,  Hak Bum CHOI ,  Hyo-Seop KIM

IPC分类号： G09G3/36

CPC分类号： G02F1/136286 ,  G02F1/13452 ,  G02F1/13458 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/1368 ,  G09G3/3648 ,  G09G3/3655 ,  G09G2300/0426 ,  G09G2300/0876 ,  G09G2320/0233 ,  H01L27/124

摘要： A display device includes gate lines, data lines, first wires and second wires extending in the directions of the gate lines and data lines, and pixels having a first subpixel and a second subpixel each. The first subpixel has a first subpixel electrode and a first switching element, and the second subpixel has a second subpixel electrode and second and third switching elements. The control terminals of the three switching elements are connected to the same gate line, and the input terminals of the first and second switching elements are connected to the same data line. The first and second switching elements have output terminals connected to the first and second subpixel electrodes, respectively. The second switching element's output terminal connects to the third switching element, which has an output terminal connected to a second wire. The first wires and the second wires are connected in a pixel.

公开(公告)号：US20120286274A1

公开(公告)日：2012-11-15

申请号：US13422686

申请日：2012-03-16

申请人： Min-Wook PARK ,  Jong-In Kim ,  Jun-Ho Song ,  Bum-Ki Baek ,  Young-Soo Yoon

发明人： Min-Wook PARK ,  Jong-In Kim ,  Jun-Ho Song ,  Bum-Ki Baek ,  Young-Soo Yoon

IPC分类号： H01L33/08

CPC分类号： H01L27/124 ,  G02F1/1362 ,  H01L27/1255

摘要： A display substrate includes a data line, a main gate line, and a first sub-pixel electrode formed on a base substrate. The display substrate further includes a first switching element connected to the data line. The display substrate further includes a second switching element connected to the data line, the main gate line, and a second sub-pixel electrode spaced apart from the first sub-pixel electrode. The display substrate further includes a third switching element connected to the data line and a secondary gate line adjacent to the main gate line. The display substrate further includes a shielding line spaced apart from the first and second sub-pixel electrodes, the shielding line overlapping the data line and receiving a reference voltage. The display substrate further includes an auxiliary electrode extending from the shielding line and overlapping an end electrode connected to the third switching element.

摘要翻译： 显示基板包括形成在基底基板上的数据线，主栅线和第一子像素电极。 显示基板还包括连接到数据线的第一开关元件。 显示基板还包括连接到数据线，主栅极线和与第一子像素电极间隔开的第二子像素电极的第二开关元件。 显示基板还包括连接到数据线的第三开关元件和与主栅极线相邻的次级栅极线。 显示基板还包括与第一和第二子像素电极间隔开的屏蔽线，屏蔽线与数据线重叠并接收参考电压。 显示基板还包括从屏蔽线延伸并与连接到第三开关元件的端电极重叠的辅助电极。

公开(公告)号：US20110156046A1

公开(公告)日：2011-06-30

申请号：US12978446

申请日：2010-12-24

申请人： Yeon-Ju KIM ,  Sung-Jae MOON ,  Yun-Jung CHO ,  Bum-Ki BAEK ,  Kwang-Hoon LEE ,  Byoung-Sun NA ,  Sung-Hoon YANG ,  Yoon-Jang KIM ,  Eun CHO

发明人： Yeon-Ju KIM ,  Sung-Jae MOON ,  Yun-Jung CHO ,  Bum-Ki BAEK ,  Kwang-Hoon LEE ,  Byoung-Sun NA ,  Sung-Hoon YANG ,  Yoon-Jang KIM ,  Eun CHO

IPC分类号： H01L29/04 ,  G03F1/00

CPC分类号： G03F1/38 ,  G03F1/00 ,  G03F1/14 ,  G03F1/36 ,  H01L29/41733

摘要： A photomask includes; a source electrode pattern including; a first electrode portion which extends in a first direction, a second electrode portion which extends in the first direction and is substantially parallel to the first electrode portion, and a third electrode portion which extends from a first end of the first electrode portion to a first end of the second electrode portion and is rounded with a first curvature, a drain electrode pattern which extends in the first direction and is disposed between the first electrode portion and the second electrode portion, wherein an end of the drain electrode pattern is rounded to correspond to the third electrode portion; and a channel region pattern which is disposed between the source electrode pattern and the drain electrode pattern, wherein a center location of the first curvature and a center location of the rounded portion of the end of the drain electrode pattern are the same.

摘要翻译： 光掩模包括 源电极图案，包括： 沿第一方向延伸的第一电极部分，沿第一方向延伸并基本上平行于第一电极部分的第二电极部分，以及从第一电极部分的第一端延伸到第一电极部分的第三电极部分， 并且以第一曲率圆形化，漏电极图案，其沿第一方向延伸并且设置在第一电极部分和第二电极部分之间，其中漏极电极图案的端部被圆化以对应 到所述第三电极部分; 以及设置在源极电极图案和漏极电极图案之间的沟道区域图案，其中第一曲率的中心位置和漏极电极图案的端部的圆形部分的中心位置相同。

公开(公告)号：US20090283769A1

公开(公告)日：2009-11-19

申请号：US12467967

申请日：2009-05-18

申请人： Woon-Yong PARK ,  Bum-Ki Baek

发明人： Woon-Yong PARK ,  Bum-Ki Baek

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： H01L27/1288 ,  G02F1/13458 ,  G02F1/136204 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/1214

摘要： A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittance between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on the position. At this time, a thin portion and a thick portion of the photoresist pattern are provided for the display area, and a thick portion and a zero thickness portion for the peripheral area. In the peripheral area, the portions of the passivation layer, the semiconductor layer and the gate insulating layer on the gate pads, and the portions of the passivation layer on the data pads, under the zero thickness portion, are removed. In the display area, the thin portion of the photoresist pattern, and the portions of the passivation layer and the semiconductor layer thereunder are removed but the portions of the passivation layer under the thick portions of the photoresist pattern is not removed. Then, a plurality of pixel electrodes, redundant gate pads and redundant data pads are formed.

摘要翻译： 在具有显示区域和周边区域的基板上形成包括显示区域中的多个栅极线和栅电极的栅极线以及周边区域中的栅极焊盘。 依次沉积栅极绝缘层，半导体层，欧姆接触层和导体层，并且对导体层和欧姆接触进行图案化以形成包括多条数据线，源电极和漏电极的数据线 的周边区域的显示区域和数据焊盘以及其下的欧姆接触层图案。 沉积钝化层，并在其上涂覆正性光致抗蚀剂层。 光致抗蚀剂层通过在显示区域和周边区域之间具有不同透射率的一个或多个掩模曝光。 光致抗蚀剂层被显影以形成具有根据位置而变化的厚度的光致抗蚀剂图案。 此时，为显示区域设置有光致抗蚀剂图形的薄部分和厚部分，并且为周边区域设置厚部分和零厚度部分。 在外围区域中，除去栅极焊盘上的钝化层，半导体层和栅极绝缘层的部分以及零厚度部分下的数据焊盘上的钝化层的部分。 在显示区域中，去除了光致抗蚀剂图案的薄部分以及钝化层和其下面的半导体层的部分，但是未除去光致抗蚀剂图案的厚部下方的钝化层的部分。 然后，形成多个像素电极，冗余栅极焊盘和冗余数据焊盘。

公开(公告)号：US07541225B2

公开(公告)日：2009-06-02

申请号：US11332076

申请日：2006-01-13

申请人： Bum-Ki Baek ,  Hyuk-Jin Kim

发明人： Bum-Ki Baek ,  Hyuk-Jin Kim

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, forming a passivation layer on the source electrode and the drain electrode, forming a photoresist film on the passivation layer, selectively etching the passivation layer using the photoresist film as a mask, forming a conductive film, and removing the photoresist film along with the conductive film disposed on the photoresist film using a CMP (chemical mechanical polishing) process to form a pixel electrode being connected to the drain electrode.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，该方法包括在衬底上形成具有栅电极，源电极和漏电极的薄膜晶体管，在源电极和漏电极上形成钝化层 在钝化层上形成光致抗蚀剂膜，使用光致抗蚀剂膜作为掩模选择性地蚀刻钝化层，形成导电膜，以及使用CMP（化学机械抛光）与设置在光致抗蚀剂膜上的导电膜一起除去光致抗蚀剂膜 ）处理以形成连接到漏电极的像素电极。

公开(公告)号：US07507994B2

公开(公告)日：2009-03-24

申请号：US11625694

申请日：2007-01-22

申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Hao ,  Jong-Soo Yoon ,  Doug-Gyu Kim

发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Hao ,  Jong-Soo Yoon ,  Doug-Gyu Kim

IPC分类号： H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.

摘要翻译： 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。

公开(公告)号：US20060194376A1

公开(公告)日：2006-08-31

申请号：US11332076

申请日：2006-01-13

申请人： Bum-Ki Baek ,  Hyuk-Jin Kim

发明人： Bum-Ki Baek ,  Hyuk-Jin Kim

IPC分类号： H01L21/84 ,  H01L31/113

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, forming a passivation layer on the source electrode and the drain electrode, forming a photoresist film on the passivation layer, selectively etching the passivation layer using the photoresist film as a mask, forming a conductive film, and removing the photoresist film along with the conductive film disposed on the photoresist film using a CMP (chemical mechanical polishing) process to form a pixel electrode being connected to the drain electrode.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，该方法包括在衬底上形成具有栅电极，源电极和漏电极的薄膜晶体管，在源电极和漏电极上形成钝化层 在钝化层上形成光致抗蚀剂膜，使用光致抗蚀剂膜作为掩模选择性地蚀刻钝化层，形成导电膜，以及使用CMP（化学机械抛光）与设置在光致抗蚀剂膜上的导电膜一起除去光致抗蚀剂膜 ）处理以形成连接到漏电极的像素电极。

公开(公告)号：US20050082535A1

公开(公告)日：2005-04-21

申请号：US10926719

申请日：2004-08-26

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： G02F1/136 ,  G02F1/133 ,  G02F1/1339 ,  G02F1/1368 ,  G03C1/85 ,  G03C5/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/336 ,  H01L29/786

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。