公开(公告)号：US07869255B2

公开(公告)日：2011-01-11

申请号：US11943657

申请日：2007-11-21

申请人： Byung Yong Choi ,  Choong Ho Lee ,  Kyu Charn Park

发明人： Byung Yong Choi ,  Choong Ho Lee ,  Kyu Charn Park

IPC分类号： G11C11/00

CPC分类号： H01L27/105 ,  H01L27/101 ,  H01L27/112

摘要： A non-volatile memory device includes a substrate having a recess thereon, a resistant material layer pattern in the recess, a lower electrode on the resistant material layer pattern in the recess, a dielectric layer, and an upper electrode formed on the dielectric layer. The resistant material layer pattern includes a material whose resistance varies according to an applied voltage. The dielectric layer is formed on the substrate, the resistant material layer pattern and the lower electrode. An upper electrode overlaps the resistant material layer pattern and the lower electrode. The applied voltage is applied to access the upper and lower electrodes to vary the resistance of the resistant material layer pattern.

摘要翻译： 非易失性存储器件包括其上具有凹部的衬底，凹部中的电阻材料层图案，凹部中的电阻材料层图案上的下电极，形成在电介质层上的电介质层和上电极。 电阻材料层图案包括其电阻根据施加的电压而变化的材料。 介电层形成在基板上，电阻材料层图案和下电极上。 上电极与电阻材料层图案和下电极重叠。 施加施加的电压以访问上电极和下电极以改变电阻材料层图案的电阻。

公开(公告)号：US07842570B2

公开(公告)日：2010-11-30

申请号：US12137976

申请日：2008-06-12

申请人： Albert Fayrushin ,  Byung-Yong Choi ,  Choong-Ho Lee

发明人： Albert Fayrushin ,  Byung-Yong Choi ,  Choong-Ho Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics.

摘要翻译： 在制造存储器件的方法中，在衬底上形成隧道绝缘层。 在隧道绝缘层上形成具有基本均匀厚度的浮栅。 在浮栅上形成介电层。 在电介质层上形成控制栅极。 包括浮动栅极的闪速存储器件可具有更均匀的操作特性。

公开(公告)号：US07760550B2

公开(公告)日：2010-07-20

申请号：US12168961

申请日：2008-07-08

申请人： Albert Fayrushin ,  Byung-Yong Choi

发明人： Albert Fayrushin ,  Byung-Yong Choi

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/3418

摘要： A method of reading data in a non-volatile memory device includes applying a bit line read voltage to a bit line and a selected cell read voltage to a word line, both of which are electrically connected to a selected cell located in a selected string. A first read voltage is applied to word lines electrically connected to first non-selected cells separated from the selected cell in the selected string, and a second read voltage is applied to word lines electrically connected to second non-selected cells adjacent to the selected cell in the selected string. The second read voltage is lower than the first read voltage. A pass voltage is applied to turn on a string select transistor and a ground select transistor, respectively, in the selected string. An electrical signal output from the selected string is compared with a standard signal to read data stored in the selected cell.

摘要翻译： 一种在非易失性存储器件中读取数据的方法包括将位线读取电压施加到位线，并将所选择的单元读取电压施加到字线，这两者都电连接到位于所选择的串中的选定单元。 将第一读取电压施加到电连接到在所选择的串中从所选择的单元分离的第一非选择单元的字线，并且将第二读取电压施加到电连接到与所选单元相邻的第二未选择单元的字线 在所选字符串中。 第二读取电压低于第一读取电压。 施加通过电压以分别在所选择的串中接通串选择晶体管和接地选择晶体管。 将从所选字符串输出的电信号与标准信号进行比较，以读取存储在所选择的单元中的数据。

公开(公告)号：US07652322B2

公开(公告)日：2010-01-26

申请号：US12014262

申请日：2008-01-15

申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

摘要翻译： 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。

公开(公告)号：US20090016110A1

公开(公告)日：2009-01-15

申请号：US12168961

申请日：2008-07-08

申请人： Byung-Yong CHOI ,  Albert FAYRUSHIN

发明人： Byung-Yong CHOI ,  Albert FAYRUSHIN

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/3418

摘要： A method of reading data in a non-volatile memory device includes applying a bit line read voltage to a bit line and a selected cell read voltage to a word line, both of which are electrically connected to a selected cell located in a selected string. A first read voltage is applied to word lines electrically connected to first non-selected cells separated from the selected cell in the selected string, and a second read voltage is applied to word lines electrically connected to second non-selected cells adjacent to the selected cell in the selected string. The second read voltage is lower than the first read voltage. A pass voltage is applied to turn on a string select transistor and a ground select transistor, respectively, in the selected string. An electrical signal output from the selected string is compared with a standard signal to read data stored in the selected cell.

摘要翻译： 一种在非易失性存储器件中读取数据的方法包括将位线读取电压施加到位线，并将所选择的单元读取电压施加到字线，这两者都电连接到位于所选择的串中的选定单元。 将第一读取电压施加到电连接到在所选择的串中从所选择的单元分离的第一非选择单元的字线，并且将第二读取电压施加到电连接到与所选单元相邻的第二未选择单元的字线 在所选字符串中。 第二读取电压低于第一读取电压。 施加通过电压以分别在所选择的串中接通串选择晶体管和接地选择晶体管。 将从所选字符串输出的电信号与标准信号进行比较，以读取存储在所选择的单元中的数据。

公开(公告)号：US20080293215A1

公开(公告)日：2008-11-27

申请号：US12219737

申请日：2008-07-28

申请人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim ,  Dong-Gun Park ,  Eun-Suk Cho ,  Suk-Kang Sung ,  Byung-Yong Choi ,  Tae-Yong Kim ,  Choong-Ho Lee

发明人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim ,  Dong-Gun Park ,  Eun-Suk Cho ,  Suk-Kang Sung ,  Byung-Yong Choi ,  Tae-Yong Kim ,  Choong-Ho Lee

IPC分类号： H01L21/76

CPC分类号： H01L29/785 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/1159 ,  H01L27/2436 ,  H01L29/66795

摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

公开(公告)号：US20080203377A1

公开(公告)日：2008-08-28

申请号：US12035169

申请日：2008-02-21

申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

IPC分类号： H01L47/00

CPC分类号： H01L45/165 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/146

摘要： Integrated circuit nonvolatile memory devices are manufactured by forming a variable resistance layer on an integrated circuit substrate. The variable resistance layer includes grains that define grain boundaries between the grains. Conductive filaments are formed along at least some of the grain boundaries. Electrodes are formed on the variable resistance layer. The conductive filaments may be formed by implanting conductive ions into at least some of the grain boundaries. Moreover, the variable resistance layer may be a variable resistance oxide of a metal, and the conductive filaments may be the metal. Related devices are also disclosed.

摘要翻译： 通过在集成电路基板上形成可变电阻层来制造集成电路非易失性存储器件。 可变电阻层包括限定晶粒之间的晶界的晶粒。 沿着至少一些晶界形成导电丝。 电极形成在可变电阻层上。 可以通过将导电离子注入至少一些晶界来形成导电细丝。 此外，可变电阻层可以是金属的可变电阻氧化物，并且导电丝可以是金属。 还公开了相关设备。

公开(公告)号：US20080164509A1

公开(公告)日：2008-07-10

申请号：US11972243

申请日：2008-01-10

申请人： Seung-Chul Lee ,  Keun-Ho Lee ,  Choong-Ho Lee ,  Byung-Yong Choi

发明人： Seung-Chul Lee ,  Keun-Ho Lee ,  Choong-Ho Lee ,  Byung-Yong Choi

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile memory device includes a semiconductor substrate of a first conductivity type, a plurality of word lines on the semiconductor substrate, each the plurality of word lines including a floating gate of a second conductivity type. A ground select line and a string select line are disposed on respective sides of word lines. An impurity region of the second conductivity type underlies a first word line adjacent the ground select line. The device may further include a second impurity region of the second conductivity type underlying a second word line adjacent the string select line. In still further embodiments, the device may further include third impurity regions of the second conductivity type underlying respective third word lines between the first word line and the second word line. Methods of forming such devices are also provided.

摘要翻译： 非易失性存储器件包括第一导电类型的半导体衬底，半导体衬底上的多个字线，多条字线包括第二导电类型的浮置栅极。 地线选择线和串选择线设置在字线的相应侧上。 第二导电类型的杂质区域位于与地选线相邻的第一字线的正下方。 该器件还可以包括第二导电类型的第二杂质区域，位于与串选择线相邻的第二字线下方。 在另外的实施例中，器件还可以包括在第一字线和第二字线之间的相应第三字线下方的第二导电类型的第三杂质区。 还提供了形成这种装置的方法。

公开(公告)号：US20080081411A1

公开(公告)日：2008-04-03

申请号：US11616582

申请日：2006-12-27

申请人： Hye-Jin Cho ,  Kyu-Charn Park ,  Choong-Ho Lee ,  Byung-Yong Choi

发明人： Hye-Jin Cho ,  Kyu-Charn Park ,  Choong-Ho Lee ,  Byung-Yong Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents-hydrogen (H) atoms from leaking into the device isolation pattern.

摘要翻译： 在制造非易失性存储器件的方法中，在衬底上形成导电结构。 导电结构包括隧道氧化物图案，第一导电图案，衬垫氧化物图案和硬掩模图案。 使用导电结构作为蚀刻掩模在衬底上形成沟槽。 在沟槽的内壁和隧道氧化物图案的侧壁和第一导电图案上形成内部氧化物层。 内部氧化物层被固化，从而在内部氧化物层上形成氮化硅层。 在沟槽中形成器件隔离图案，并且从衬底去除硬掩模图案和衬垫氧化物图案。 在基板上形成电介质层和第二导电图案。 因此，氮化硅层防止氢（H）原子泄漏到器件隔离图案中。

公开(公告)号：US20070090449A1

公开(公告)日：2007-04-26

申请号：US11580086

申请日：2006-10-13

申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Dong-Gun Park

发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Dong-Gun Park

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.

摘要翻译： 提供了一种非易失性存储器件及其形成方法。 非易失性存储器件可以包括依次层叠在半导体衬底的预定或给定区域上的单元隔离图案和半导体图案，半导体图案上的单元栅极线和半导体衬底的一侧的顶表面上的半导体图案 电池隔离图案，单元栅极线和半导体衬底之间的多层陷阱绝缘层，以及单元栅极线和半导体图案，在单元栅极线的两侧的半导体衬底中的第一杂质扩散层和 位于单元栅极线两侧的半导体图案中的第二杂质扩散层。