Methods for identifying allosteric and other novel acyl-coenzyme A:cholesterol acyltransferase inhibitors
    2.
    发明授权
    Methods for identifying allosteric and other novel acyl-coenzyme A:cholesterol acyltransferase inhibitors 失效
    用于鉴别变构和其他新型酰基辅酶A:胆固醇酰基转移酶抑制剂的方法

    公开(公告)号:US08673587B2

    公开(公告)日:2014-03-18

    申请号:US13639141

    申请日:2011-05-03

    CPC classification number: C12Q1/48 G01N2333/91057 G01N2500/02

    Abstract: The present invention is a method for identifying compounds that are allosteric and/or other novel ACAT inhibitors that is based on the novel finding that pregnenolone is a substrate for ACAT; esterification of pregnenolone by ACAT is dramatically activated when cholesterol is present in the assay. The method comprises measuring the esterification of pregnenolone by ACAT under two different conditions: with cholesterol, or without cholesterol. This method can be used to test and categorize various candidate ACAT inhibitors as allosteric or other novel ACAT inhibitors, or it can be used in high-throughput screening for identifying such ACAT inhibitors.

    Abstract translation: 本发明是一种鉴别化合物的方法,该化合物是基于新戊酸烯醇酮是ACAT底物的新发现的变构型和/或其它新型ACAT抑制剂。 当胆固醇存在于测定中时,ACAT的孕烯醇酮酯化剧烈活化。 该方法包括通过ACAT在两种不同条件下测定孕烯醇酮的酯化:用胆固醇或不含胆固醇。 该方法可用于测试和分类各种候选ACAT抑制剂作为变构或其他新型ACAT抑制剂,或者可用于高通量筛选鉴定此类ACAT抑制剂。

    Process related deviation corrected parasitic capacitance modeling method
    3.
    发明授权
    Process related deviation corrected parasitic capacitance modeling method 失效
    过程相关偏差纠正寄生电容建模方法

    公开(公告)号:US07028277B2

    公开(公告)日:2006-04-11

    申请号:US10326500

    申请日:2002-12-20

    CPC classification number: G06F17/5036

    Abstract: Each of a method for determining a parasitic capacitance and an apparatus for determining the parasitic capacitance provides for an experimental correlation within a parasitic capacitance model of a series of conductor layer nominal dimensions and spacings with a process related deviation to provide a series of conductor layer actual dimensions and spacings. The method and the apparatus further provide for determining the parasitic capacitance while employing the conductor layer actual dimensions and spacings. The parasitic capacitance is thus determined with enhanced accuracy.

    Abstract translation: 用于确定寄生电容的方法和用于确定寄生电容的装置中的每一个提供了在一系列导体层标称尺寸和间隔的寄生电容模型内的与过程相关偏差的实验相关性,以提供一系列导体层实际 尺寸和间距。 该方法和装置进一步提供了在采用导体层的实际尺寸和间距的同时确定寄生电容。 因此,寄生电容的精度提高。

    Methodology to characterize metal sheet resistance of copper damascene process
    4.
    发明授权
    Methodology to characterize metal sheet resistance of copper damascene process 失效
    表征铜镶嵌工艺金属薄层电阻的方法

    公开(公告)号:US06854100B1

    公开(公告)日:2005-02-08

    申请号:US10228496

    申请日:2002-08-27

    CPC classification number: G06F17/5036

    Abstract: A new method to determine a parameter of a damascene interconnect in an integrated circuit device is achieved. Drawn dimensions and local pattern density of a damascene interconnect are extracted in an integrated circuit device. A parameter of the damascene interconnect is calculating using the drawn dimensions and the local pattern density to select a per unit value from a set of per unit values measured over a range of drawn dimension and pattern density combinations. The method may be used to improve the accuracy of extracted damascene metal line resistance and parasitic capacitance.

    Abstract translation: 实现了一种确定集成电路器件中的镶嵌互连参数的新方法。 在集成电路器件中提取镶嵌互连的拉丝尺寸和局部图案密度。 大马士革互连的参数是使用绘制的尺寸和局部图案密度来计算,以从在拉伸尺寸和图案密度组合的范围上测量的每单位值的集合中选择每单位值。 该方法可用于提高提取的镶嵌金属线电阻和寄生电容的精度。

    Metal Thickness Simulation for Improving RC Extraction Accuracy
    10.
    发明申请
    Metal Thickness Simulation for Improving RC Extraction Accuracy 审中-公开
    提高RC提取精度的金属厚度模拟

    公开(公告)号:US20070266360A1

    公开(公告)日:2007-11-15

    申请号:US11688692

    申请日:2007-03-20

    CPC classification number: G06F17/5081 G06F2217/12 Y02P90/265

    Abstract: An integrated circuit (IC) design method includes providing a design layout defined in a plurality of grids; simulating a chemical mechanical polishing (CMP) process to an IC substrate with a patterned structure defined by the design layout, generating a dielectric thickness and a metal thickness on one of the plurality of grids; extracting a capacitance based on the dielectric thickness on the one of the plurality of grids; and extracting a resistance based on the metal thickness on the one of the plurality of grids.

    Abstract translation: 集成电路(IC)设计方法包括提供在多个网格中定义的设计布局; 模拟化学机械抛光(CMP)工艺到具有由设计布局限定的图案化结构的IC衬底,在所述多个栅格之一上产生电介质厚度和金属厚度; 基于所述多个栅格中的所述一个栅极上的电介质厚度提取电容; 以及基于所述多个网格中的所述一个网格上的金属厚度提取电阻。

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