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    CHIP PACKAGE STRUCTURE
    2.
    发明申请
    CHIP PACKAGE STRUCTURE 审中-公开
    芯片包装结构

    公开(公告)号：US20050224936A1

    公开(公告)日：2005-10-13

    申请号：US10907675

    申请日：2005-04-12

    Applicant: Jeng-Dah Wu ,  Yi-Shao Lai ,  Chang-Lin Yeh

    Inventor： Jeng-Dah Wu ,  Yi-Shao Lai ,  Chang-Lin Yeh

    IPC: H01L23/02 ,  H01L23/28 ,  H01L23/31

    CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A chip package includes a package substrate, a chip and a molding compound. The package substrate has a carrying surface and a back surface opposite to the carrying surface. The chip is mounted on the carrying surface and electrically connected to the package substrate. Furthermore, the molding compound is applied over the carrying surface to cover the chip and a part of the package substrate. The outline of a juncture between the molding compound and the package substrate is a smooth closed curve so that thermal stress is uniformly distributed over the juncture to prevent stress concentration. The reliability of the package structure is thereby improved.

    Abstract translation: 芯片封装包括封装基板，芯片和模塑料。 封装基板具有承载表面和与承载表面相对的后表面。 芯片安装在承载表面上并电连接到封装基板。 此外，将模塑料涂覆在承载表面上以覆盖芯片和封装基板的一部分。 模塑料与封装基板之间的连接处的轮廓是平滑的闭合曲线，使得热应力均匀地分布在接合部上以防止应力集中。 由此提高了封装结构的可靠性。

    Bonding strength testing device
    4.
    发明授权
    Bonding strength testing device 有权
    粘接强度试验装置

    公开(公告)号：US07329900B2

    公开(公告)日：2008-02-12

    申请号：US11306900

    申请日：2006-01-16

    Applicant: Chang-Lin Yeh ,  Yi-Shao Lai

    Inventor： Chang-Lin Yeh ,  Yi-Shao Lai

    IPC: H01L23/58

    CPC classification number: G01N19/04 ,  G01N3/00 ,  G01N3/30 ,  G01N2203/0039

    Abstract: A bonding strength test device suits to perform a bonding strength test for at least one solder ball that fixed on a substrate. The bonding strength test device includes a fixed base and an impact apparatus. The impact apparatus has a first end and a second end corresponding to the first end. While an impact is applied to the first end of the impact apparatus, the impact apparatus moves downward, and the second end of the impact apparatus hits the solder ball on the substrate for performing the bonding strength test. Besides, the fixed base is used for limiting the downward movement of the impact apparatus.

    Abstract translation: 接合强度测试装置适用于对固定在基板上的至少一个焊球执行接合强度测试。 接合强度试验装置包括固定基座和撞击装置。 冲击装置具有对应于第一端的第一端和第二端。 当冲击装置施加到冲击装置的第一端时，撞击装置向下移动，并且冲击装置的第二端撞击基板上的焊球以进行粘接强度试验。 此外，固定底座用于限制冲击装置的向下运动。

    Semiconductor package structure
    5.
    发明申请
    Semiconductor package structure 审中-公开
    半导体封装结构

    公开(公告)号：US20070222047A1

    公开(公告)日：2007-09-27

    申请号：US11602383

    申请日：2006-11-21

    Applicant: Tsung-Yueh Tsai ,  Chang-Lin Yeh

    Inventor： Tsung-Yueh Tsai ,  Chang-Lin Yeh

    IPC: H01L23/02

    CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/31 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A semiconductor package structure includes a substrate, a first chip, a second chip, a wire, and an encapsulant. The substrate with a cavity has a first surface and a second surface. The cavity penetrates the first surface and the second surface. The first surface and the second surface have a first solder pad and a second solder pad respectively. The first chip having a first active surface and a first non-active surface is disposed inside the cavity. The first active surface has a first contact pad. The second chip having a second active surface and a second non-active surface is disposed on the second surface. The second non-active surface is adhered to the first non-active surface. The second active surface has a second contact pad. The wire is used for electrically connecting the second contact pad and the second solder pad. The encapsulant disposed on the substrate fills the cavity.

    Abstract translation: 半导体封装结构包括衬底，第一芯片，第二芯片，导线和密封剂。 具有空腔的基板具有第一表面和第二表面。 空腔穿透第一表面和第二表面。 第一表面和第二表面分别具有第一焊盘和第二焊盘。 具有第一活性表面和第一非活性表面的第一芯片设置在腔内。 第一活性表面具有第一接触垫。 具有第二活性表面和第二非活性表面的第二芯片设置在第二表面上。 第二非活性表面粘附到第一非活性表面。 第二活动表面具有第二接触垫。 电线用于电连接第二接触焊盘和第二焊盘。 设置在基板上的密封剂填充空腔。

    BONDING STRENGTH TESTING DEVICE
    6.
    发明申请
    BONDING STRENGTH TESTING DEVICE 有权
    粘结强度测试装置

    公开(公告)号：US20060231834A1

    公开(公告)日：2006-10-19

    申请号：US11306900

    申请日：2006-01-16

    Applicant: Chang-Lin Yeh ,  Yi-Shao Lai

    Inventor： Chang-Lin Yeh ,  Yi-Shao Lai

    IPC: H01L23/58

    CPC classification number: G01N19/04 ,  G01N3/00 ,  G01N3/30 ,  G01N2203/0039

    Abstract: A bonding strength test device suits to perform a bonding strength test for at least one solder ball that fixed on a substrate. The bonding strength test device includes a fixed base and an impact apparatus. The impact apparatus has a first end and a second end corresponding to the first end. While an impact is applied to the first end of the impact apparatus, the impact apparatus moves downward, and the second end of the impact apparatus hits the solder ball on the substrate for performing the bonding strength test. Besides, the fixed base is used for limiting the downward movement of the impact apparatus.

    Abstract translation: 接合强度测试装置适用于对固定在基板上的至少一个焊球执行接合强度测试。 接合强度试验装置包括固定基座和撞击装置。 冲击装置具有对应于第一端的第一端和第二端。 当冲击装置施加到冲击装置的第一端时，撞击装置向下移动，并且冲击装置的第二端撞击基板上的焊球以进行粘接强度试验。 此外，固定底座用于限制冲击装置的向下运动。

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