公开(公告)号：US08421242B2

公开(公告)日：2013-04-16

申请号：US12651087

申请日：2009-12-31

申请人： Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Yi-Shao Lai ,  Chang-Lin Yeh ,  Ming-Hsiang Cheng

发明人： Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Yi-Shao Lai ,  Chang-Lin Yeh ,  Ming-Hsiang Cheng

IPC分类号： H01L23/48

CPC分类号： H01L23/16 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/562 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.

摘要翻译： 提供半导体封装。 半导体封装包括有机衬底，刚度层和芯片子组件。 刚性层形成在有机基底上。 芯片组件设置在刚度层上。 芯片子组件至少包括第一芯片，第二芯片和第三芯片。 第二芯片以堆叠取向布置在第一芯片和第三芯片之间。 第一芯片，第二芯片和第三芯片具有接近通信的功能。

公开(公告)号：US08274149B2

公开(公告)日：2012-09-25

申请号：US12749191

申请日：2010-03-29

申请人： Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Yi-Shao Lai ,  Ming-Hsiang Cheng

发明人： Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Yi-Shao Lai ,  Ming-Hsiang Cheng

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L21/563 ,  H01L23/48 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/30155 ,  H01L2224/30181 ,  H01L2224/73103 ,  H01L2224/73153 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92143 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are disposed on and electrically connected to the first surface and around the cavity. The active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure. The bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.

摘要翻译： 公开了一种半导体器件封装及其制造方法。 半导体器件封装包括衬底，缓冲结构，两个有源芯片和桥接芯片。 衬底具有空腔，第一表面和与第一表面相对的第二表面。 空腔从第一表面延伸到第二表面，并且缓冲结构设置在空腔中。 有源芯片设置在第一表面上并且电连接到第一表面并且围绕空腔。 活性芯片都具有第一活性表面。 桥芯片设置在空腔中并在缓冲结构上方。 桥芯片具有第二有源表面，第二有源表面面向第一有源表面并且与第一有源表面部分地重叠，桥芯片用于提供有源芯片之间的邻近通信。

公开(公告)号：US08222733B2

公开(公告)日：2012-07-17

申请号：US12729034

申请日：2010-03-22

申请人： Ming-Hsiang Cheng ,  Yi-Shao Lai ,  Tsung-Yueh Tsai ,  Hsiao-Chuan Chang

发明人： Ming-Hsiang Cheng ,  Yi-Shao Lai ,  Tsung-Yueh Tsai ,  Hsiao-Chuan Chang

IPC分类号： H01L23/00 ,  H01L21/50

CPC分类号： H01L25/0652 ,  H01L23/053 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19105

摘要： A first substrate has a first surface facing a second surface of the second substrate. The active chips are disposed on and electrically connected to the first surface, and spaced apart from each other by an interval, wherein the active chips respectively have a first active surface. The bridge chip is mechanically and electrically connected to the second surface, and has a second active surface partially overlapped with the first active surfaces of the active chips, such that the bridge chip is used for providing a proximity communication between the active chips. The connection structure is disposed between the first surface and the second surface for combining the first substrate and the second substrate.

摘要翻译： 第一基板具有面向第二基板的第二表面的第一表面。 有源芯片设置在第一表面上并电连接到第一表面，并且间隔彼此间隔开，其中有源芯片分别具有第一有源表面。 桥芯片机械地和电连接到第二表面，并且具有与有源芯片的第一有源表面部分地重叠的第二有源表面，使得桥接芯片用于提供有源芯片之间的邻近通信。 连接结构设置在第一表面和第二表面之间，用于组合第一基板和第二基板。

公开(公告)号：US20120139143A1

公开(公告)日：2012-06-07

申请号：US13079816

申请日：2011-04-05

申请人： Tun-Fun Way ,  Kai-Jen Hsiao ,  Shi-Kuang Hwang ,  Jiun-Jy Chen ,  Hsiao-Chuan Chang ,  Yu-Ting Chen

发明人： Tun-Fun Way ,  Kai-Jen Hsiao ,  Shi-Kuang Hwang ,  Jiun-Jy Chen ,  Hsiao-Chuan Chang ,  Yu-Ting Chen

IPC分类号： D01F9/12 ,  C08L35/04 ,  C08F222/30

CPC分类号： D01F6/54 ,  C08L33/20 ,  D01F1/10 ,  D01F9/22

摘要： A plasticizing agent and a composition for fabricating a polyacrylonitrile-based fiber precursor and a fabrication method of a polyacrylonitrile-based carbon fiber are provided. The plasticizing agent includes a copolymer represented by formula (I) or a derivative of formula (I): wherein R is methyl or ethyl, z≧0.5 mol %, and y=99.5-85.0 mol %. The plasticizing agent has an intrinsic viscosity of between 0.20-0.40 dL/g. The composition for fabricating the polyacrylonitrile-based fiber precursor includes the plasticizing agent and a polyacrylonitrile-based copolymer having an intrinsic viscosity of between 0.41-0.75 dL/g.

摘要翻译： 提供增塑剂和用于制备聚丙烯腈类纤维前体的组合物和聚丙烯腈类碳纤维的制造方法。 增塑剂包括由式（I）表示的共聚物或式（I）的衍生物：其中R是甲基或乙基，z≥0.5mol％，y = 99.5-85.0mol％。 增塑剂的特性粘度在0.20-0.40dL / g之间。 用于制造聚丙烯腈基纤维前体的组合物包括增塑剂和特性粘度在0.41-0.75dL / g之间的聚丙烯腈类共聚物。

公开(公告)号：US08115285B2

公开(公告)日：2012-02-14

申请号：US12192805

申请日：2008-08-15

申请人： Chien-Wen Chen ,  Yi-Shao Lai ,  Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Hsu-Yang Lee

发明人： Chien-Wen Chen ,  Yi-Shao Lai ,  Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Hsu-Yang Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.

摘要翻译： 描述半导体封装和相关方法。 在一个实施例中，封装包括管芯焊盘，多个引线，芯片，封装体和保护层。 管芯焊盘包括上倾斜部分，下倾斜部分和限定具有空腔底部的空腔的周边边缘区域。 每个引线包括上倾斜部分和下倾斜部分。 芯片设置在腔体底部并耦合到引线。 封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。 芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。 保护层基本上覆盖至少一个引线的下倾斜部分和下表面。

公开(公告)号：US08110931B2

公开(公告)日：2012-02-07

申请号：US12501246

申请日：2009-07-10

申请人： Hsiao Chuan Chang ,  Tsung Yueh Tsai ,  Yi Shao Lai ,  Ho Ming Tong ,  Jian Cheng Chen ,  Wei Chi Yih ,  Chang Ying Hung ,  Cheng Wei Huang ,  Chih Hsing Chen ,  Tai Yuan Huang ,  Chieh Ting Chen ,  Yi Tsai Lu

发明人： Hsiao Chuan Chang ,  Tsung Yueh Tsai ,  Yi Shao Lai ,  Ho Ming Tong ,  Jian Cheng Chen ,  Wei Chi Yih ,  Chang Ying Hung ,  Cheng Wei Huang ,  Chih Hsing Chen ,  Tai Yuan Huang ,  Chieh Ting Chen ,  Yi Tsai Lu

IPC分类号： H01L23/48

CPC分类号： H01L24/85 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05169 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05672 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48453 ,  H01L2224/48465 ,  H01L2224/48507 ,  H01L2224/48609 ,  H01L2224/48611 ,  H01L2224/48618 ,  H01L2224/48623 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48649 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48666 ,  H01L2224/48669 ,  H01L2224/48672 ,  H01L2224/48809 ,  H01L2224/48818 ,  H01L2224/48823 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48849 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48866 ,  H01L2224/48872 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85043 ,  H01L2224/85045 ,  H01L2224/85201 ,  H01L2224/85375 ,  H01L2224/8581 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/00 ,  H01L2224/48811 ,  H01L2224/48869 ,  H01L2924/00012

摘要： A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.

摘要翻译： 晶片限定以阵列方式布置的多个芯片。 每个芯片包括至少一个铝焊盘和中间材料。 中间材料覆盖铝垫，并安装在铝垫上。

公开(公告)号：US07964949B2

公开(公告)日：2011-06-21

申请号：US12216637

申请日：2008-07-09

申请人： Yi-Shao Lai ,  Tsung-Yueh Tsai ,  Hsiao-Chuan Chang ,  Tsan-Hsien Chen

发明人： Yi-Shao Lai ,  Tsung-Yueh Tsai ,  Hsiao-Chuan Chang ,  Tsan-Hsien Chen

IPC分类号： H01L23/02

CPC分类号： H01L23/3107 ,  H01L25/03 ,  H01L25/16 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.

摘要翻译： 提供包括载体和芯片的榫眼包装结构。 载体具有与顶表面相对的顶表面和下表面。 顶表面形成至少一个榫头突起，并且下表面形成对应于形状，尺寸和位置的榫头突起的榫槽，使得两个载体可以通过将榫头投影连接到彼此并且彼此连接 相应的榫槽。 榫头和榫槽分别具有导电部分。 当榫头突起和榫槽彼此接合时，导电部分彼此电连接。 至少一个芯片嵌入在载体中。 芯片分别具有有源表面和背面，并与载体的顶表面和下表面电连接。

公开(公告)号：US20100007011A1

公开(公告)日：2010-01-14

申请号：US12501693

申请日：2009-07-13

申请人： Chang Ying HUNG ,  Hsiao Chuan Chang ,  Tsung Yueh Tsai ,  Yi Shao Lai ,  Jian Cheng Chen ,  Wei Chi Yih ,  Ho Ming Tong

发明人： Chang Ying HUNG ,  Hsiao Chuan Chang ,  Tsung Yueh Tsai ,  Yi Shao Lai ,  Jian Cheng Chen ,  Wei Chi Yih ,  Ho Ming Tong

IPC分类号： H01L23/488 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L24/85 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85043 ,  H01L2224/85045 ,  H01L2224/85201 ,  H01L2224/92247 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.

摘要翻译： 引线键合结构包括芯片和接合线。 芯片包括基材，至少一个第一金属垫，再分布层和至少一个第二金属垫。 第一金属垫设置在基材上。 再分布层具有第一端和第二端，并且第一端电连接到第一金属垫。 第二金属垫电连接到再分配层的第二端。 接合线接合到第二金属垫。

公开(公告)号：US08368216B2

公开(公告)日：2013-02-05

申请号：US12872644

申请日：2010-08-31

申请人： Yi-Shao Lai ,  Tsung-Yueh Tsai ,  Ming-Kun Chen ,  Hsiao-Chuan Chang ,  Ming-Hsiang Cheng

发明人： Yi-Shao Lai ,  Tsung-Yueh Tsai ,  Ming-Kun Chen ,  Hsiao-Chuan Chang ,  Ming-Hsiang Cheng

IPC分类号： H01L23/538 ,  H01L21/60 ,  H01L23/488

CPC分类号： H01L21/6835 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/27 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/1184 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/16145 ,  H01L2224/2784 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/831 ,  H01L2225/06513 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/014

摘要： The present invention relates to a semiconductor package having at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface upon which the first metal bumps are disposed and a plurality of first signal coupling pads disposed adjacent to the first active surface. The second layer chip is electrically connected to the first layer chip, and includes a second active surface that faces the first active surface and a plurality of second signal coupling pads. The second signal coupling pads are capacitively coupled to the first signal coupling pads so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps, and the second layer chip, and the first metal bumps are partially exposed.

摘要翻译： 本发明涉及具有至少一个第一层芯片，多个第一金属凸块，至少一个第二层芯片和封装体的半导体封装。 第一层芯片包括设置有第一金属凸块的第一有源表面和与第一有源表面相邻设置的多个第一信号耦合焊盘。 第二层芯片电连接到第一层芯片，并且包括面向第一有源表面的第二有源表面和多个第二信号耦合焊盘。 第二信号耦合焊盘电容耦合到第一信号耦合焊盘，以便提供第一层芯片和第二层芯片之间的接近通信。 封装体封装第一层芯片，第一金属凸块和第二层芯片，并且第一金属凸块部分地露出。

公开(公告)号：US20110278739A1

公开(公告)日：2011-11-17

申请号：US12777442

申请日：2010-05-11

申请人： Yi-Shao Lai ,  Tsung-Yueh Tsai ,  Ming-Kun Chen ,  Hsiao-Chuan Chang ,  Ming-Hsiang Cheng

发明人： Yi-Shao Lai ,  Tsung-Yueh Tsai ,  Ming-Kun Chen ,  Hsiao-Chuan Chang ,  Ming-Hsiang Cheng

IPC分类号： H01L23/52

CPC分类号： H01L23/49827 ,  H01L23/147 ,  H01L23/48 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1815 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and an interposer. The first chip is mechanically and electrically connected to the substrate. Some signal pads of the interposer are capacitively coupled to some signal pads of the first chip, so as to provide proximity communication between the first chip and the interposer. Whereby, the capacitively coupled signal pads can be made in fine pitch, and therefore the size of the semiconductor package is reduced and the density of the signal pads is increased.

摘要翻译： 本发明涉及半导体封装。 半导体封装包括衬底，第一芯片和插入器。 第一芯片机械地和电连接到基板。 插入器的一些信号焊盘电容耦合到第一芯片的一些信号焊盘，以便在第一芯片和插入器之间提供接近通信。 由此，电容耦合的信号焊盘可以以细间距制成，因此半导体封装的尺寸减小，信号焊盘的密度增加。