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    Ferroelectric materials and ferroelectric memory device made therefrom
    1.
    发明授权
    Ferroelectric materials and ferroelectric memory device made therefrom 有权
    铁电材料和由其制成的铁电存储器件

    公开(公告)号：US07307304B2

    公开(公告)日：2007-12-11

    申请号：US11150854

    申请日：2005-06-09

    Applicant: Tai-Bor Wu ,  Cheng-Lung Hung

    Inventor： Tai-Bor Wu ,  Cheng-Lung Hung

    IPC: H01L29/76

    CPC classification number: H01L21/02197 ,  H01L21/31691 ,  H01L28/55 ,  H01L29/516

    Abstract: A ferroelectric material includes a compound of formula (I): (Pb1−x−zBazAx)(ByZr1−y)O3,   (I) wherein 0≦x≦0.1, 0≦y≦0.020, 0.15≦z≦0.35, with the proviso that y≠0 when x=0, and that x≠0, when y=0; and wherein A is a first element having a valence number greater than that of Pb, and B is a second element having a valence number greater than that of Zr. A ferroelectric memory device made from the ferroelectric material is also disclosed.

    Abstract translation: 铁电材料包括式（I）的化合物：<？in-line-formula description =“In-line Formulas”end =“lead”→>（Pb 1-xz Ba （B）Z 1，Y 3，X 3，X 3，X 3， <？in-line-formula description =“In-line Formulas”end =“tail”？>其中0 <= x <= 0.1,0 <= y <= 0.020,0.15 <= z <= 0.35，附带条件 当x = 0时y <> 0，当y = 0时x <> 0; 并且其中A是具有大于Pb的价数的第一元素，B是具有大于Zr的价数的第二元素。 还公开了由铁电材料制成的铁电存储器件。

    Ferroelectric material and ferroelectric memory device made therefrom
    4.
    发明申请
    Ferroelectric material and ferroelectric memory device made therefrom 有权
    铁电材料和由其制成的铁电存储器件

    公开(公告)号：US20050285171A1

    公开(公告)日：2005-12-29

    申请号：US11150854

    申请日：2005-06-09

    Applicant: Tai-Bor Wu ,  Cheng-Lung Hung

    Inventor： Tai-Bor Wu ,  Cheng-Lung Hung

    IPC: C04B35/491 ,  H01L21/02 ,  H01L21/316 ,  H01L27/20 ,  H01L29/51 ,  H01L29/76

    CPC classification number: H01L21/02197 ,  H01L21/31691 ,  H01L28/55 ,  H01L29/516

    Abstract: A ferroelectric material includes a compound of formula (I): (Pb1-x-zBazAx) (ByZr1-y)O3  (I) wherein 0≦x≦0.1, 0≦y≦0.020, 0.15≦z≦0.35, with the proviso that y≠0 when x=0, and that x≠0, when y=0; and wherein A is a first element having a valence number greater than that of Pb, and B is a second element having a valence number greater than that of Zr. A ferroelectric memory device made from the ferroelectric material is also disclosed.

    Abstract translation: 铁电材料包括式（I）的化合物：<？in-line-formula description =“In-line Formulas”end =“lead”→>（Pb 1-xz Ba （I）（A）其中R 1，R 2，R 3，R 3，R 5， ？in-line-formula description =“In-line Formulas”end =“tail”？>其中0 <= x <= 0.1,0 <= y <= 0.020,0.15 <= z <= 0.35，条件是 当x = 0时，y <> 0，当y = 0时x <> 0; 并且其中A是具有大于Pb的价数的第一元素，B是具有大于Zr的价数的第二元素。 还公开了由铁电材料制成的铁电存储器件。

    Method for forming a dielectric-constant-enchanced capacitor
    5.
    发明授权
    Method for forming a dielectric-constant-enchanced capacitor 有权
    形成介电常数增强电容器的方法

    公开(公告)号：US06640403B2

    公开(公告)日：2003-11-04

    申请号：US09866468

    申请日：2001-05-29

    Applicant: Wong-Cheng Shih ,  Lan Lin Chao ,  Tai-Bor Wu ,  Chich-Shang Chang

    Inventor： Wong-Cheng Shih ,  Lan Lin Chao ,  Tai-Bor Wu ,  Chich-Shang Chang

    IPC: H01G700

    CPC classification number: H01L28/40 ,  H01L21/3143 ,  H01L21/31604 ,  Y10T29/43 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

    Abstract: A method for forming a dielectric-constant-enhanced capacitor is provided. A wafer in a reaction chamber is provided, wherein said wafer comprises a first conductive layer. Then, a first dielectric layer is formed above said first conductive layer to prevent said first conductive layer from growing silicon oxide and to diminish leakage current. Next a precursor is transmitted to a vaporizer. Then said precursor is transformed to a gas and said gas is transmitted to said reaction chamber. Next, a second dielectric layer is deposited above said first dielectric layer. Then a heat treatment is proceeded and a second conductive layer is formed on said second dielectric layer.

    Abstract translation: 提供一种形成介电常数增强电容器的方法。 提供反应室中的晶片，其中所述晶片包括第一导电层。 然后，在所述第一导电层之上形成第一电介质层，以防止所述第一导电层生长氧化硅并且减小漏电流。 接下来，将前体传送到蒸发器。 然后将所述前体转化为气体，所述气体被传递到所述反应室。 接下来，在所述第一介电层上沉积第二电介质层。 然后进行热处理，在所述第二电介质层上形成第二导电层。

    Method for forming patterned modified metal layer
    6.
    发明申请
    Method for forming patterned modified metal layer 审中-公开
    形成图案改性金属层的方法

    公开(公告)号：US20110011148A1

    公开(公告)日：2011-01-20

    申请号：US12585721

    申请日：2009-09-23

    Applicant: Sun-Zen Chen ,  Tai-Bor Wu ,  Ching-Wen Chang ,  Wen-Feng Kuo ,  Ruo-Ying Wu

    Inventor： Sun-Zen Chen ,  Tai-Bor Wu ,  Ching-Wen Chang ,  Wen-Feng Kuo ,  Ruo-Ying Wu

    IPC: B21D22/00

    CPC classification number: B44C1/20

    Abstract: A method for forming a patterned modified metal layer is disclosed, which comprises the following steps: (A) providing a metal base which is in the form of either a bulk metal or a metal coated substrate, and a mold with patterns; (B) applying the mold onto the metal base to transfer the patterns of the mold to the metal surface; (C) removing the mold; and (D) modifying the whole metal base or the, surface and a certain depth beneath the surface of metal base to form a modified metal layer with designated patterns.

    Abstract translation: 公开了一种用于形成图案化的改性金属层的方法，其包括以下步骤：（A）提供呈块状金属或金属涂覆的基底的形式的金属基底和具有图案的模具; （B）将模具施加到金属基底上以将模具的图案转移到金属表面; （C）取出模具; 和（D）改变整个金属基底或金属基底表面下方的一定深度以形成具有指定图案的改性金属层。

    Resistive memory device having enhanced resist ratio and method of manufacturing same
    7.
    发明申请
    Resistive memory device having enhanced resist ratio and method of manufacturing same 有权
    具有增强的抗蚀剂比率的电阻式存储器件及其制造方法

    公开(公告)号：US20080266931A1

    公开(公告)日：2008-10-30

    申请号：US11739942

    申请日：2007-04-25

    Applicant: Denny Tang ,  Tai-Bor Wu ,  Wen-Yuan Chang ,  Tzyh-Cheang Lee

    Inventor： Denny Tang ,  Tai-Bor Wu ,  Wen-Yuan Chang ,  Tzyh-Cheang Lee

    IPC: G11C11/24 ,  G11C11/00

    CPC classification number: G11C11/16 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/55

    Abstract: Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this unique stack structure have revealed a resistance ratio of approximately 1000× over conventional electrode-dielectric-electrode stack structures found in resistive memory devices. This improvement in the resistance ratio of the resistive memory device is believed to be from the improved interface coherence, and thus smoother topography, between the buffer layer(s) and the dielectric layer.

    Abstract translation: 这里公开了具有包围介电层的一个或多个缓冲层的新的电阻式存储器件。 通过在器件的介电层周围插入一个或多个缓冲层，器件的电阻比被高度提高。 例如，使用这种独特的堆叠结构的测试显示出比电阻式存储器件中发现的常规电极 - 电介质电极堆叠结构大约1000倍的电阻比。 电阻式存储器件的电阻比的这种改进被认为是来自缓冲层和电介质层之间的改进的界面相干性，从而更平滑的形貌。

    Semiconductor device and method for forming the same
    8.
    发明申请
    Semiconductor device and method for forming the same 审中-公开
    半导体装置及其形成方法

    公开(公告)号：US20070012977A1

    公开(公告)日：2007-01-18

    申请号：US11522593

    申请日：2006-09-18

    Applicant: Tai-Bor Wu ,  Chun-Kai Huang

    Inventor： Tai-Bor Wu ,  Chun-Kai Huang

    IPC: H01L29/94 ,  H01L21/00

    CPC classification number: H01L28/40 ,  H01L27/11502

    Abstract: A semiconductor device includes a MOS transistor having a capacitor-forming surface; and a ferroelectric capacitor formed on the capacitor-forming surface of the MOS transistor and including upper and lower electrode layers of Pt and a dielectric layer sandwiched between the upper and lower electrode layers. The ferroelectric capacitor has a cross-section that is generally trapezoid in shape, and that has an inclined side which forms an angle of greater than 45 degrees and less than 90 degrees with the capacitor-forming surface of the MOS transistor.

    Abstract translation: 半导体器件包括具有电容器形成表面的MOS晶体管; 以及形成在MOS晶体管的电容器形成表面上的铁电电容器，并且包括Pt的上下电极层和夹在上电极层和下电极层之间的电介质层。 强电介质电容器具有通常为梯形的横截面，并且具有与MOS晶体管的电容器形成表面形成大于45度且小于90度的角度的倾斜侧。

    Resistive memory device having enhanced resist ratio and method of manufacturing same
    10.
    发明授权
    Resistive memory device having enhanced resist ratio and method of manufacturing same 有权
    具有增强的抗蚀剂比率的电阻式存储器件及其制造方法

    公开(公告)号：US07579612B2

    公开(公告)日：2009-08-25

    申请号：US11739942

    申请日：2007-04-25

    Applicant: Denny Tang ,  Tai-Bor Wu ,  Wen-Yuan Chang ,  Tzyh-Cheang Lee

    Inventor： Denny Tang ,  Tai-Bor Wu ,  Wen-Yuan Chang ,  Tzyh-Cheang Lee

    IPC: H01L47/00

    CPC classification number: G11C11/16 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/55

    Abstract: Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this unique stack structure have revealed a resistance ratio of approximately 1000× over conventional electrode-dielectric-electrode stack structures found in resistive memory devices. This improvement in the resistance ratio of the resistive memory device is believed to be from the improved interface coherence, and thus smoother topography, between the buffer layer(s) and the dielectric layer.

    Abstract translation: 这里公开了具有包围介电层的一个或多个缓冲层的新的电阻式存储器件。 通过在器件的介电层周围插入一个或多个缓冲层，器件的电阻比被高度提高。 例如，使用这种独特的堆叠结构的测试显示出比电阻式存储器件中发现的常规电极 - 电介质电极堆叠结构大约1000倍的电阻比。 电阻式存储器件的电阻比的这种改进被认为是来自缓冲层和电介质层之间的改进的界面相干性，从而更平滑的形貌。

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