公开(公告)号：USD690133S1

公开(公告)日：2013-09-24

申请号：US29417487

申请日：2012-04-04

Applicant: Cheng-Ming Wu

Designer： Cheng-Ming Wu

公开(公告)号：US06727029B1

公开(公告)日：2004-04-27

申请号：US10336550

申请日：2003-01-02

Applicant: Cheng-Ming Wu ,  Paul Chu ,  Chiou-Sung Chiu ,  Chih-Wing Chang

Inventor： Cheng-Ming Wu ,  Paul Chu ,  Chiou-Sung Chiu ,  Chih-Wing Chang

IPC: G03F900

CPC classification number: G03F1/64

Abstract: A reticle for holding a mask thereon with reduced particle contamination problem is described. The reticle is constructed by a base plate that is formed of an optically transparent material such as quartz and has a recessed slot in a top surface to enclose an area at least the size of a mask formed on the base plate. An adhesive partially fills the recessed slot such that a top surface of the adhesive is at least 0.5 mm below the top surface of the base plate. A pellicle frame is mounted in the recessed slot with a bottom end of the frame encased in the adhesive and a thin film covering the top end of the pellicle frame to from a hermetically sealed cavity for protecting the mask.

Abstract translation: 描述了用于在其上保持减少的颗粒污染问题的掩模上的掩模版。 掩模版由基板构成，该基板由诸如石英的光学透明材料形成，并且在顶表面中具有凹槽，以至少包围形成在基板上的掩模的尺寸的区域。 粘合剂部分地填充凹槽，使得粘合剂的顶表面在基板的顶表面下方至少0.5mm。 防护薄膜组件框架安装在凹槽中，框架的底端封装在粘合剂中，并且薄膜覆盖防护薄膜组件框架的顶端，以从密封的腔体中保护面罩。

公开(公告)号：US06168989A

公开(公告)日：2001-01-02

申请号：US09318924

申请日：1999-05-26

Applicant: Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu

Inventor： Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu

IPC: H01L218242

CPC classification number: H01L28/91 ,  H01L27/10814

Abstract: A method for making crown capacitors using a new and improved crown etch window process for DRAM cells is described. After forming FETs for the memory cells, a planar first insulating layer (IPO-1) is formed and bit lines are formed thereon. A second insulating layer (IPO-2) is deposited, and a first etch-stop layer and a disposable insulating layer are deposited. Contact openings are etched in the layers to the substrate, and are filled with a polysilicon to form capacitor node contact plugs. The disposable layer is removed to expose the upper portions of the plugs extending above the first etch-stop layer. A second etch-stop layer is deposited and a thick insulating layer is deposited in which capacitor openings are etched over and to the plugs. The capacitor openings can be over-etched in the thick insulating layer because the plugs extend upward thereby allowing all the plugs to be exposed across the wafer without overetching the underlying IPO-2 layer that would otherwise cause capacitor-to-bit-line shorts when the bottom electrodes are formed in the capacitor openings.

Abstract translation: 描述了使用用于DRAM单元的新的和改进的冠蚀刻窗口工艺制造冠电容器的方法。 在形成用于存储单元的FET之后，形成平面的第一绝缘层（IPO-1），并在其上形成位线。 沉积第二绝缘层（IPO-2），并沉积第一蚀刻停止层和一次性绝缘层。 接触开口在层中蚀刻到衬底上，并且填充有多晶硅以形成电容器节点接触插塞。 去除一次性层以暴露在第一蚀刻停止层上方延伸的插塞的上部。 沉积第二蚀刻停止层，并且沉积厚的绝缘层，其中电容器开口被蚀刻到插头上。 电容器开口可以在厚的绝缘层中过蚀刻，因为插头向上延伸，从而允许所有的插头暴露在晶片上，而不会过滤掉底层的IPO-2层，否则会导致电容器对位线短路， 底部电极形成在电容器开口中。

公开(公告)号：US6080647A

公开(公告)日：2000-06-27

申请号：US34927

申请日：1998-03-05

Applicant: Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

Inventor： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

IPC: H01L21/336 ,  H01L21/768 ,  H01L21/3205

CPC classification number: H01L29/6659 ,  H01L21/76895 ,  H01L29/66545

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

Abstract translation: 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。 介电材料层沉积在衬底上以填充间隙。 去除了掩模层。 此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 将离子注入到开口内的半导体衬底中以形成掩埋接触。 选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。 电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US6042999A

公开(公告)日：2000-03-28

申请号：US73952

申请日：1998-05-07

Applicant: Cheng-Tung Lin ,  Yu-Hua Lee ,  Jenn Ming Huang ,  Cheng-Ming Wu

Inventor： Cheng-Tung Lin ,  Yu-Hua Lee ,  Jenn Ming Huang ,  Cheng-Ming Wu

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/26

CPC classification number: H01L21/76808 ,  G03F7/0035 ,  H01L21/0276

Abstract: A robust dual damascene process is disclosed where the substructure in a substrate is protected from damage caused by multiple etchings required in a damascene process by filling a contact or via hole opening with a protective material prior to the forming of the conductive line opening of the damascene structure having an etch-stop layer separating a lower and an upper dielectric layer. In the first embodiment, the protective material is partially removed from the hole opening reaching the substructure prior to the forming of the upper conductive line opening by etching. In the second embodiment, the protective material in the hole is removed at the same time the upper conductive line opening is formed by etching. In a third embodiment, the disclosed process is applied without the need of an etch-stop layer for the dual damascene process of this invention.

Abstract translation: 公开了一种稳健的双镶嵌工艺，其中通过在形成镶嵌导电线开口之前通过填充具有保护材料的接触或通孔开口来保护衬底中的子结构免受由镶嵌工艺中所需的多次蚀刻所造成的损伤 具有分隔下电介质层和上电介质层的蚀刻停止层的结构。 在第一实施例中，在通过蚀刻形成上导电线开口之前，保护材料部分地从到达底层结构的开孔中去除。 在第二实施例中，在通过蚀刻形成上导电线开口的同时去除孔中的保护材料。 在第三个实施例中，应用所公开的工艺，而不需要用于本发明的双镶嵌工艺的蚀刻停止层。

公开(公告)号：US6015734A

公开(公告)日：2000-01-18

申请号：US148561

申请日：1998-09-04

Applicant: Kuo Ching Huang ,  Yu Hua Lee ,  Cheng-Ming Wu

Inventor： Kuo Ching Huang ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A new method for forming stacked capacitors for DRAMs having improved yields when the bottom electrode is misaligned to the node contact is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer, a Si.sub.3 N.sub.4 etch-stop layer, and a disposable second insulating layer are deposited. First openings for node contacts are etched in the insulating layers. A polysilicon layer is deposited and etched back to form node contacts in the first openings. The node contacts are recessed in the second insulating layer, but above the etch-stop layer to form node contacts abutting the etch-stop layer. A disposable third SiO.sub.2 layer is deposited. Second openings for bottom electrodes are etched over and to the node contacts. A conformal second polysilicon layer is deposited and chem/mech polished back to form the bottom electrodes in the second openings. The third and second insulating layers are removed by wet etching to the etch-stop layer. When the second openings are misaligned over the node contact openings, the polysilicon plugs abutting the Si.sub.3 N.sub.4 etch-stop layer protect the SiO.sub.2 first insulating layer from being eroded over the devices on the substrate. The capacitors are completed by forming a thin dielectric layer on the bottom electrodes, and forming top electrodes from a patterned third polysilicon layer.

Abstract translation: 实现了当底电极不对准节点接触时，用于形成具有提高的产量的DRAM的叠层电容器的新方法。 沉积平面氧化硅（SiO 2）第一绝缘层，Si 3 N 4蚀刻停止层和一次性第二绝缘层。 在绝缘层中蚀刻用于节点接触的第一开口。 沉积多晶硅层并回蚀刻以在第一开口中形成节点接触。 节点触点凹陷在第二绝缘层中，但在蚀刻停止层之上，以形成邻接蚀刻停止层的节点触点。 沉积一次性第三SiO 2层。 底部电极的第二个开口被蚀刻到节点触点上。 沉积保形的第二多晶硅层，并在第二开口中化学/机械抛光以形成底部电极。 第三绝缘层和第二绝缘层通过湿法蚀刻去除蚀刻停止层。 当第二开口在节点接触开口上不对准时，邻接Si 3 N 4蚀刻停止层的多晶硅栓保护SiO 2第一绝缘层免受衬底上的器件的侵蚀。 通过在底部电极上形成薄的电介质层，并从图案化的第三多晶硅层形成顶部电极来完成电容器。

公开(公告)号：US06235580B1

公开(公告)日：2001-05-22

申请号：US09467123

申请日：1999-12-20

Applicant: Yu-Hua Lee ,  Cheng-Ming Wu ,  Wen-Chuan Chiang

Inventor： Yu-Hua Lee ,  Cheng-Ming Wu ,  Wen-Chuan Chiang

IPC: H01L218242

CPC classification number: H01L27/10852 ,  H01L28/91

Abstract: A process for forming crown shaped capacitor structures, for a DRAM device, has been developed. The process features the use of a disposable insulator layer, applied prior to photolithographic and dry etching procedures, used to define the capacitor upper plate structures. The disposable insulator layer alleviates the topography effects presented by crown shaped storage node structures, relaxing the complexity of the patterning of the capacitor upper plate structures.

Abstract translation: 已经开发了用于形成用于DRAM器件的冠形电容器结构的工艺。 该方法的特征在于使用一次性绝缘体层，其在光刻和干蚀刻工艺之前施加，用于限定电容器上板结构。 一次性绝缘体层减轻了冠形存储节点结构呈现的形貌效应，减轻了电容器上板结构图案化的复杂性。

公开(公告)号：US5989784A

公开(公告)日：1999-11-23

申请号：US55463

申请日：1998-04-06

Applicant: Yu-Hua Lee ,  Cheng-Ming Wu ,  Chao-Cheng Chen

Inventor： Yu-Hua Lee ,  Cheng-Ming Wu ,  Chao-Cheng Chen

IPC: H01L21/768 ,  H01L23/525 ,  G03F7/40 ,  B44C1/22 ,  C03C15/00 ,  C25F3/00

CPC classification number: H01L23/5258 ,  H01L21/76802 ,  H01L2924/0002

Abstract: A method of forming an etch stop layer 40 above a fuse 16 in a fuse opening (or window) 92 using a specialized 2 stage etch process. The invention has two important features: First, the etch stop layer 40 is formed from a polysilicon layer (P2 or P4) that is used to fabricate semiconductor devices on a substrate. The etch stop layer 40 is preferably formed of polysilicon layer to is used to from a contact to the substrate 10 (P2) or to form part of a capacitor (P4). Second, a specialized two stage etch process is used where the second stage etches the etch stop layer 40 while simultaneously forming a passivation layer 114 over a metal pad 85. The method comprises: forming fuses 16 over said isolation regions 10 over the fuse area 15; forming a first dielectric layer 30 overlying the fuses 16; forming an etch stop layer 40 over the first dielectric layer 30; forming an insulating layer 43 over the etch stop layer; forming a fuse opening 92 in the insulating layer 43 by etching, in a first etch stage, thorough fuse photoresist openings 90A and stopping the first etch stage on the etch stop layer 40; and etching though the etch stop layer 40 in the fuse opening 92 in a second etch stage.

Abstract translation: 使用专门的2级蚀刻工艺在保险丝开口（或窗口）92中的熔丝16上方形成蚀刻停止层40的方法。 本发明具有两个重要特征：首先，蚀刻停止层40由用于在基板上制造半导体器件的多晶硅层（P2或P4）形成。 蚀刻停止层40优选由多晶硅层形成，用于从接触到衬底10（P2）或形成电容器（P4）的一部分。 第二，使用专门的两级蚀刻工艺，其中第二阶段蚀刻蚀刻停止层40，同时在金属焊盘85上形成钝化层114.该方法包括：在保险丝区域15上方的所述隔离区域10上形成保险丝16 ; 形成覆盖保险丝16的第一电介质层30; 在第一介电层30上形成蚀刻停止层40; 在所述蚀刻停止层上形成绝缘层43; 在绝缘层43中通过在第一蚀刻阶段中蚀刻完整的熔融光致抗蚀剂开口90A并停止蚀刻停止层40上的第一蚀刻阶段来在绝缘层43中形成熔丝开口92; 并且在第二蚀刻阶段通过熔丝开口92中的蚀刻停止层40进行蚀刻。

公开(公告)号：US5985765A

公开(公告)日：1999-11-16

申请号：US75368

申请日：1998-05-11

Applicant: Yung-Kuan Hsiao ,  Cheng-Ming Wu ,  Yu-Hua Lee

Inventor： Yung-Kuan Hsiao ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/525 ,  H01L21/00

CPC classification number: H01L24/02 ,  H01L23/5256 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14

Abstract: A method for reducing bonding pad loss is achieved using a capping layer when contact openings are etched to the bonding pads, while concurrently etching much deeper fuse openings to the substrate. Bonding pads are used on the top surface of integrated circuit semiconductor chips to provide external electrical connections for I/Os and power. And fuses are used in the underlying insulating layers to remove redundant defective circuit elements and thereby repair defective chips. It is desirable (cost effective) to etch the contact openings in the passivation layer to the bonding pads near the top surface on the chip and to concurrently etch the much deeper fuse openings in the thick underlying insulating layers over the fuses. However, because of the difference in etch depth of the two types of openings, the bonding pads composed of Al/Cu are generally overetched causing bond-pad reliability problems. This invention uses a novel process in which a capping layer, having a low etch rate, is formed on the bonding pads to prevent overetching while the fuse openings are etched to the desired depth in the thicker insulating layers.

Abstract translation: 当接触开口被蚀刻到接合焊盘时，使用覆盖层来实现减少焊盘损耗的方法，同时将更深的熔丝开口蚀刻到衬底。 在集成电路半导体芯片的顶面上使用接合焊盘以提供用于I / O和电源的外部电连接。 并且在底层绝缘层中使用熔丝来去除冗余的有缺陷的电路元件，从而修复有缺陷的芯片。 将钝化层中的接触开口蚀刻到芯片顶表面附近的接合焊盘是合乎需要的（成本有效的），同时蚀刻保险丝上较厚的下层绝缘层中更深的熔丝开口。 然而，由于两种类型的开口的蚀刻深度的差异，由Al / Cu组成的焊盘通常是过蚀刻的，导致焊盘可靠性问题。 本发明使用了一种新颖的方法，其中在焊盘上形成具有低蚀刻速率的覆盖层，以防止在较厚绝缘层中将熔丝开口蚀刻到所需深度时的过蚀刻。

公开(公告)号：US08820385B2

公开(公告)日：2014-09-02

申请号：US13468299

申请日：2012-05-10

Applicant: Cheng-Ming Wu

Inventor： Cheng-Ming Wu

IPC: E06B9/305

CPC classification number: E06B9/322 ,  E06B2009/3222

Abstract: Disclosed is a control device for a cordless blind with willful stop at any positions according to user needs during switching operation. The control device primarily comprises a force-return mechanism, a shaft connector, and a braking buffer mechanism which are all installed inside a same housing. The force-return mechanism has a flat spring bevel gear and an elastic element. One end of the shaft connector is a transmission bevel gear meshed with the flat spring bevel gear. The braking buffer mechanism includes a friction ring and an impeding spring where the friction ring is immovably fixed inside the housing with a wear-proof annular inwall. The impeding spring is tightly plugged into the friction ring with an extrusion to prevent the rotation of the transmission bevel gear. Specifically, the shaft connector has a trigger to change the friction between the impeding spring and the friction ring.

Abstract translation: 本发明公开了一种无绳盲板的控制装置，其在切换操作期间根据用户需要在任意位置故意停止。 控制装置主要包括一个力回复机构，一个轴连接器和一个制动缓冲机构，它们均安装在同一个外壳内。 力回复机构具有扁平的弹簧锥齿轮和弹性元件。 轴连接器的一端是与扁平弹簧伞齿轮啮合的传动伞齿轮。 制动缓冲机构包括摩擦环和阻挡弹簧，其中摩擦环通过耐磨环形壁固定在壳体内。 阻碍弹簧用挤压件紧密地插入摩擦环中，以防止变速器锥齿轮的旋转。 具体地，轴连接器具有用于改变阻力弹簧和摩擦环之间的摩擦力的触发器。