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    METHODS FOR FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHODS FOR FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE 有权
    形成半导体器件精细图案的方法

    公开(公告)号：US20160042965A1

    公开(公告)日：2016-02-11

    申请号：US14822438

    申请日：2015-08-10

    Applicant: SoonMok Ha ,  Sung-Wook Hwang ,  Joonsoo Park ,  Dae-Yong Kang ,  Byungjun Jeon

    Inventor： SoonMok Ha ,  Sung-Wook Hwang ,  Joonsoo Park ,  Dae-Yong Kang ,  Byungjun Jeon

    IPC: H01L21/308

    CPC classification number: H01L21/0271 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338

    Abstract: The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns.

    Abstract translation: 本发明构思提供了形成半导体器件精细图案的方法。 该方法包括在包括第一区域的硬掩模层和在第一区域周围的第二区域的硬掩模层上形成具有第一孔的缓冲掩模层，形成填充第一孔的第一柱并且设置在第一区域中的缓冲掩模层上， 设置在第二区域中的缓冲掩模层上，形成覆盖缓冲掩模层上的第一和第二柱的嵌段共聚物层，相分离嵌段共聚物层以形成与第一和第二柱间隔开的第一嵌段图案和 围绕第一和第二柱和第一块图案的第二块图案，去除第一块图案，以及在第一块图案之下在缓冲掩模层中形成第二孔。

    METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING CONTACT HOLES
    4.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING CONTACT HOLES 有权
    形成接触孔的半导体器件的方法

    公开(公告)号：US20160260632A1

    公开(公告)日：2016-09-08

    申请号：US15049989

    申请日：2016-02-22

    Applicant: Dae-Yong KANG ,  Eunsung Kim ,  Byungjun Jeon ,  Joonsoo Park ,  Soonmok Ha

    Inventor： Dae-Yong KANG ,  Eunsung Kim ,  Byungjun Jeon ,  Joonsoo Park ,  Soonmok Ha

    IPC: H01L21/768 ,  H01L27/108 ,  H01L27/115 ,  H01L21/311 ,  H01L21/3105

    CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76816 ,  H01L27/10847 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a stopper layer on a target layer including a cell area and an edge area, forming a hard mask including first upper openings and dam trench on the stopper layer, forming opening spacers on inner walls of the first upper openings and a dam pattern in the dam trench, removing the stopper layer exposed in the first upper openings to form first lower openings, forming pillar patterns in the first lower openings and the first upper openings and an eaves pattern on the dam pattern, removing the hard mask in the cell area, forming a first polymer block between the pillar patterns including second upper openings, etching the stopper layer exposed in the second upper openings to form second lower openings, and removing the first polymer block, the pillar patterns, the dam pattern and the eaves pattern.

    Abstract translation: 提供制造半导体器件的方法。 所述方法可以包括在包括电池区域和边缘区域的靶层上形成阻挡层，在阻挡层上形成包括第一上部开口和阻塞沟槽的硬掩模，在第一上部开口的内壁上形成开口间隔件，以及 去除在第一上部开口中暴露的止挡层，形成第一下部开口，在第一下部开口中形成柱状图案，将第一上部开口和坝形图案上的檐形图案，去除硬掩模 在所述电池区域之间形成包括第二上部开口的所述柱状图案之间的第一聚合物嵌段，蚀刻暴露在所述第二上部开口中的所述阻挡层以形成第二下部开口，以及移除所述第一聚合物块，所述支柱图案， 屋檐模式。

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