公开(公告)号：US11822474B2

公开(公告)日：2023-11-21

申请号：US17830257

申请日：2022-06-01

申请人： FLC Global, Ltd.

发明人： Sehat Sutardja

IPC分类号： G06F12/0811 ,  G06F12/0864 ,  G11C11/406 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/10 ,  G06F12/1027 ,  G06F9/4401 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/06

CPC分类号： G06F12/0811 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0638 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0683 ,  G06F9/4406 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/10 ,  G06F12/1027 ,  G11C11/40607 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/161 ,  G06F2212/171 ,  G06F2212/20 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/251 ,  G06F2212/305 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/6022 ,  G06F2212/6032 ,  G06F2212/62 ,  Y02D10/00

摘要： A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

公开(公告)号：US20230049799A1

公开(公告)日：2023-02-16

申请号：US17830257

申请日：2022-06-01

申请人： FLC Global, Ltd.

发明人： Sehat Sutardja

IPC分类号： G06F12/0811 ,  G06F12/0864 ,  G11C11/406 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/10 ,  G06F12/1027 ,  G06F9/4401 ,  G06F12/0813 ,  G06F12/0862

摘要： A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

公开(公告)号：US10684949B2

公开(公告)日：2020-06-16

申请号：US15934886

申请日：2018-03-23

申请人： FLC Global, Ltd.

发明人： Sehat Sutardja

IPC分类号： G06F12/06 ,  G06F12/0811 ,  G06F12/0864 ,  G11C11/406 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/10 ,  G06F12/1027 ,  G06F9/4401 ,  G06F12/0813 ,  G06F12/0862

摘要： A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

公开(公告)号：US20240193084A1

公开(公告)日：2024-06-13

申请号：US18504545

申请日：2023-11-08

申请人： FLC Global, Ltd.

发明人： Sehat Sutardja

IPC分类号： G06F12/0811 ,  G06F3/06 ,  G06F9/4401 ,  G06F12/06 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/10 ,  G06F12/1027 ,  G11C11/406

CPC分类号： G06F12/0811 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0638 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0683 ,  G06F9/4406 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/10 ,  G06F12/1027 ,  G11C11/40607 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/161 ,  G06F2212/171 ,  G06F2212/20 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/251 ,  G06F2212/305 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/6022 ,  G06F2212/6032 ,  G06F2212/608 ,  G06F2212/62 ,  Y02D10/00

摘要： A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

公开(公告)号：US11360894B2

公开(公告)日：2022-06-14

申请号：US16875870

申请日：2020-05-15

申请人： FLC Global, Ltd.

发明人： Sehat Sutardja

IPC分类号： G06F12/0811 ,  G06F12/0864 ,  G11C11/406 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/10 ,  G06F12/1027 ,  G06F9/4401 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/06

摘要： A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

公开(公告)号：US20200301836A1

公开(公告)日：2020-09-24

申请号：US16875870

申请日：2020-05-15

申请人： FLC Global, Ltd.

发明人： Sehat Sutardja

IPC分类号： G06F12/0811 ,  G06F3/06 ,  G06F9/4401 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/10 ,  G06F12/1027 ,  G11C11/406

摘要： A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

公开(公告)号：US20180293167A1

公开(公告)日：2018-10-11

申请号：US15934886

申请日：2018-03-23

申请人： FLC Global, Ltd.

发明人： Sehat Sutardja

IPC分类号： G06F12/0811 ,  G11C11/406 ,  G06F12/0864 ,  G06F12/0862 ,  G06F12/0813 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/0897 ,  G06F9/4401 ,  G06F3/06 ,  G06F12/0868 ,  G06F12/0804

摘要： A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.