公开(公告)号：US20160154742A1

公开(公告)日：2016-06-02

申请号：US14862745

申请日：2015-09-23

申请人： Gad Sheaffer ,  Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann

发明人： Gad Sheaffer ,  Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann

IPC分类号： G06F12/10 ,  G06F13/16

CPC分类号： G06F12/1027 ,  G06F12/0804 ,  G06F12/126 ,  G06F13/1663 ,  G06F2212/303 ,  G06F2212/657 ,  G06F2212/684

摘要： A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing unit (GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. The device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.

摘要翻译： 计算机系统可以支持一种或多种技术来允许由诸如图形处理单元（GPU）的非CPU设备访问的存储器页的动态固定。 非CPU可以支持虚拟到物理地址映射，并且因此可以知道可能不被固定但可被非CPU访问的存储器页。 非CPU可以向诸如与CPU相关联的设备驱动程序的运行时组件通知或发送这样的信息。 设备驱动程序可以动态地执行可由非CPU访问的这种存储器页的钉扎。 设备驱动程序甚至可以取消内存页，这可能不再被非CPU访问。 这样的方法可以允许非CPU可以不再访问的存储器页面可用于分配给其他CPU和/或非CPU。

公开(公告)号：US09100938B2

公开(公告)日：2015-08-04

申请号：US13817926

申请日：2012-05-09

申请人： Shmuel Ur ,  Gad Sheaffer

发明人： Shmuel Ur ,  Gad Sheaffer

IPC分类号： H04B7/14 ,  H04W4/00 ,  H04W76/02 ,  H04W88/04

CPC分类号： H04W76/02 ,  H04W76/10 ,  H04W88/04

摘要： In one example of digital relay for out of network devices, a communications device includes a detecting component configured to detect that one or more communication endpoints is within communication range, a message receiving component configured to receive a digital message from a first communication endpoint, and a message relaying component configured to transmit the digital message to the second communication endpoint, wherein the first communication endpoint and the second communication endpoint are not communicatively coupled to each other.

摘要翻译： 在网络设备的数字中继的一个示例中，通信设备包括被配置为检测一个或多个通信端点在通信范围内的检测组件，被配置为从第一通信端点接收数字消息的消息接收组件，以及 消息中继组件，被配置为将数字消息发送到第二通信端点，其中第一通信端点和第二通信端点不通信地彼此耦合。

公开(公告)号：US20150039869A1

公开(公告)日：2015-02-05

申请号：US13956495

申请日：2013-08-01

申请人： Koichi Yamada ,  GAD SHEAFFER ,  JAN GRAY ,  LANDY WANG ,  MARTIN TAILLEFER ,  ARUN KISHAN ,  ALI-REZA ADL-TABATABAI ,  DAVID CALLAHAN

发明人： Koichi Yamada ,  GAD SHEAFFER ,  JAN GRAY ,  LANDY WANG ,  MARTIN TAILLEFER ,  ARUN KISHAN ,  ALI-REZA ADL-TABATABAI ,  DAVID CALLAHAN

IPC分类号： G06F9/38

CPC分类号： G06F9/467 ,  G06F9/30076 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861

摘要： In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在执行无界事务存储器（UTM）事务期间经由用户线程的环转移以内核模式接收控制的方法，更新与相关联的事务状态寄存器（TSR）相关联的事务状态寄存器（TSR）的状态 用户线程和用户线程的上下文存储TSR，然后在从内核模式到用户线程的转换期间恢复上下文。 以这种方式，UTM事务可以继续恢复用户线程。 描述和要求保护其他实施例。

公开(公告)号：US08370577B2

公开(公告)日：2013-02-05

申请号：US12493165

申请日：2009-06-26

申请人： Gad Sheaffer ,  David Callahan ,  Jan Gray ,  Ali-Reza Adl-Tabatabai ,  Shlomo Raikin

发明人： Gad Sheaffer ,  David Callahan ,  Jan Gray ,  Ali-Reza Adl-Tabatabai ,  Shlomo Raikin

IPC分类号： G06F12/00

CPC分类号： G06F17/30997 ,  G06F12/0802 ,  G06F12/109

摘要： Storing metadata that is disjoint from corresponding data by storing the metadata to the same address as the corresponding data but in a different address space. A metadata store instruction includes a storage address for the metadata. The storage address is the same address as that for data corresponding to the metadata, but the storage address when used for the metadata is implemented in a metadata address space while the storage address, when used for the corresponding data is implemented in a different data address space. As a result of executing the metadata store instruction, the metadata is stored at the storage address. A metadata load instruction includes the storage address for the metadata. As a result of executing the metadata load instruction, the metadata stored at the address is received. Some embodiments may further implement a metadata clear instruction which clears any entries in the metadata address space.

摘要翻译： 通过将元数据存储到与相应数据相同的地址但在不同的地址空间中，存储与相应数据不相关的元数据。 元数据存储指令包括元数据的存储地址。 存储地址与对应于元数据的数据的地址相同，但是当用于元数据的存储地址被实现在元数据地址空间中，而当用于相应数据的存储地址被实现在不同的数据地址 空间。 作为执行元数据存储指令的结果，元数据被存储在存储地址处。 元数据加载指令包括元数据的存储地址。 作为执行元数据加载指令的结果，接收存储在地址处的元数据。 一些实施例可以进一步实现清除元数据地址空间中的任何条目的元数据清除指令。

公开(公告)号：US08341356B2

公开(公告)日：2012-12-25

申请号：US13099479

申请日：2011-05-03

申请人： Shlomo Raikin ,  Shay Gueron ,  Gad Sheaffer

发明人： Shlomo Raikin ,  Shay Gueron ,  Gad Sheaffer

IPC分类号： G06F12/06

CPC分类号： G06F12/0802 ,  G06F12/0804 ,  G06F12/1491 ,  G06F21/10

摘要： Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.

摘要翻译： 本发明的实施例提供了一种安全编程范例和受保护的高速缓存，其使得处理器能够处理秘密/专用信息，同时防止恶意应用程序通过规避其他保护机制来访问该信息。 受保护的缓存可以用作构建块，以增强试图创建，管理和保护安全数据的应用程序的安全性。 描述和要求保护其他实施例。

公开(公告)号：US20120179875A1

公开(公告)日：2012-07-12

申请号：US13346987

申请日：2012-01-10

申请人： Bratin Saha ,  Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Quinn Jacobson

发明人： Bratin Saha ,  Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Quinn Jacobson

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/14 ,  G06F8/458 ,  G06F9/52 ,  G06F9/522 ,  G06F12/0802 ,  G06F12/1483

摘要： A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have an arbitrary size, is associated with a filter word. The filter word is in a first default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access, such as a first read, from the data object, access barrier operations including an ephemeral/private store operation to set the filter word to a second state are performed. Upon a subsequent/redundant access, such as a second read, the access barrier operations are elided to accelerate the subsequent access, based on the filter word being set to the second state to indicate a previous access occurred.

摘要翻译： 这里描述了用于硬件加速软件事务存储器系统中的细粒度过滤的方法和装置。 可以具有任意大小的数据对象与过滤字相关联。 当在事务的挂起期间没有发生来自数据对象的访问（例如读取）时，过滤器字处于第一默认状态。 在从数据对象遇到诸如第一次读取的第一次访问时，执行包括将过滤词设置为第二状态的临时/私人存储操作的访问障碍操作。 在诸如第二次读取的后续/冗余访问之后，基于滤波器字被设置为第二状态来指示先前访问发生，访问屏障操作被消除以加速后续访问。

公开(公告)号：US07975129B2

公开(公告)日：2011-07-05

申请号：US12562457

申请日：2009-09-18

申请人： Shlomo Raikin ,  Gad Sheaffer ,  Doron Orenstlen

发明人： Shlomo Raikin ,  Gad Sheaffer ,  Doron Orenstlen

IPC分类号： G06F9/312

CPC分类号： G06F9/3004 ,  G06F9/30087 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/526

摘要： Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.

摘要翻译： 描述了控制重排序缓冲器（ROB）以选择性地执行功能性硬件锁定禁止（HLD）。 一个设备实施例包括一个单元，以使得ROB能够在识别与关键部分（CS）入口点相关联的锁定获取操作（LAO）时选择性地禁用锁定，该选择单元选择性地退出LAO，该单元使得ROB 选择性地禁用该锁，以及一个单元来窥探缓冲区。 该设备可以基于窥探，选择性地中止与CS相关联的事务。

公开(公告)号：US20110145516A1

公开(公告)日：2011-06-16

申请号：US12638098

申请日：2009-12-15

申请人： Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Bratin Saha ,  Jan Gray ,  David Callahan ,  Burton Smith ,  Graefe Goetz

发明人： Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Bratin Saha ,  Jan Gray ,  David Callahan ,  Burton Smith ,  Graefe Goetz

IPC分类号： G06F12/00

CPC分类号： G06F9/522 ,  G06F8/458 ,  G06F9/52 ,  G06F11/3471 ,  G06F2201/865 ,  G06F2201/87

摘要： A method and apparatus for accelerating a Software Transactional Memory (STM) system is herein described. A data object and metadata for the data object may each be associated with a filter, such as a hardware monitor or ephemerally held filter information. The filter is in a first, default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access to the metadata, such as a first read, access barrier operations, such as logging of the metadata; setting a read monitor; or updating ephemeral filter information with an ephemeral/buffered store operation, are performed. Upon a subsequent/redundant access to the metadata, such as a second read, access barrier operations are elided to accelerate the subsequent access based on the filter being set to the second state to indicate a previous access occurred. Additionally, mapping of data objects to ephemeral information may be provided by software, such as through a pointer to the ephemeral information associated with the data object; an offset from a base address of the data object to the ephemeral information included associated with the data object; an index into a segment containing the ephemeral information associated with the data object; mapping the data object to the ephemeral information utilizing address arithmetic; and a hash that maps the data object to ephemeral information.

摘要翻译： 这里描述了用于加速软件事务存储器（STM）系统的方法和装置。 数据对象和数据对象的元数据可以分别与诸如硬件监视器或者瞬时保持的过滤器信息的过滤器相关联。 过滤器处于第一个默认状态，当事务的挂起期间没有发生来自数据对象的访问，例如读取。 在遇到元数据的首次访问时，例如第一读取，访问屏障操作，诸如记录元数据; 设置一个读取监视器; 或者用临时/缓冲存储操作来更新临时过滤器信息。 在对诸如第二读取的元数据的后续/冗余访问（例如第二读取）时，消除访问屏障操作以基于被设置为第二状态的过滤器来加速后续访问，以指示先前的访问发生。 另外，数据对象到短暂信息的映射可以由软件提供，例如通过指向与数据对象相关联的短暂信息的指针; 从数据对象的基地址到包括与数据对象相关联的临时信息的偏移; 指向包含与数据对象相关联的短暂信息的段的索引; 使用地址算术将数据对象映射到临时信息; 以及将数据对象映射到临时信息的散列。

公开(公告)号：US20110145304A1

公开(公告)日：2011-06-16

申请号：US12638929

申请日：2009-12-15

申请人： Jan Gray ,  Martin Taillefer ,  Yosseff Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod K. Grover ,  Michael Magruder ,  Gad Sheaffer

发明人： Jan Gray ,  Martin Taillefer ,  Yosseff Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod K. Grover ,  Michael Magruder ,  Gad Sheaffer

IPC分类号： G06F17/00 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/3834 ,  G06F9/467 ,  G06F12/0253 ,  G06F12/0815 ,  G06F12/082

摘要： Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. Embodiments includes acts for writing to a card table outside of a transaction; handling garbage collection compaction occurring when a hardware transaction is active by using a common global variable and instructing one or more agents to write to the common global variable any time an operation is performed which may change an object's virtual address; acts for managing a thread-local allocation context; acts for handling exceptions while in a hardware assisted transaction. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.

摘要翻译： 在硬件辅助交易中处理垃圾收集和异常。 实施例在包括硬件辅助交易系统的计算环境中实现。 实施例包括用于在事务之外写入卡表的动作; 通过使用公共全局变量来处理在硬件事务处于活动状态时发生的垃圾收集压缩，并且在每次执行可能改变对象的虚拟地址的操作时，指示一个或多个代理写入公共全局变量; 用于管理线程本地分配上下文的动作; 在硬件辅助交易中处理异常的行为。 一种方法包括开始硬件辅助事务，在硬件辅助事务中引发异常，包括创建异常对象，确定事务应该回滚，并且由于确定事务应该回滚，因此， 异常对象出来的硬件辅助事务。

公开(公告)号：US20100332753A1

公开(公告)日：2010-12-30

申请号：US12493163

申请日：2009-06-26

申请人： Jan Gray ,  David Callahan ,  Burton Jordan Smith ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai ,  Bratin Saha

发明人： Jan Gray ,  David Callahan ,  Burton Jordan Smith ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai ,  Bratin Saha

IPC分类号： G06F12/02 ,  G06F1/32 ,  G06F12/08

CPC分类号： G06F12/0831 ,  G06F1/3225

摘要： Synchronizing threads on loss of memory access monitoring. Using a processor level instruction included as part of an instruction set architecture for a processor, a read, or write monitor to detect writes, or reads or writes respectively from other agents on a first set of one or more memory locations and a read, or write monitor on a second set of one or more different memory locations are set. A processor level instruction is executed, which causes the processor to suspend executing instructions and optionally to enter a low power mode pending loss of a read or write monitor for the first or second set of one or more memory locations. A conflicting access is detected on the first or second set of one or more memory locations or a timeout is detected. As a result, the method includes resuming execution of instructions.

摘要翻译： 在内存访问监控丢失时同步线程。 使用处理器级指令作为处理器，读取或写入监视器的指令集体系结构的一部分而被包括，以分别从第一组一个或多个存储器位置和读取的或其他存储器位置的其他代理检测写入或读取或写入 设置在第二组一个或多个不同存储单元上的写监视器。 执行处理器级指令，这使得处理器暂停执行指令，并且可选地进入低功率模式，等待丢失第一或第二组一个或多个存储器位置的读或写监视器。 在一个或多个存储器位置的第一或第二组上检测到冲突的访问，或者检测到超时。 结果，该方法包括恢复指令的执行。