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    Circuit for rotating, left shifting, or right shifting bits
    1.
    发明授权
    Circuit for rotating, left shifting, or right shifting bits 失效
    旋转，左移或右移位的电路

    公开(公告)号：US5978822A

    公开(公告)日：1999-11-02

    申请号：US581047

    申请日：1995-12-29

    申请人： Jumana A. Muwafi ,  Gerhard Fettweis ,  Howard W. Neff

    发明人： Jumana A. Muwafi ,  Gerhard Fettweis ,  Howard W. Neff

    IPC分类号： G06F5/01 ,  G06F7/76 ,  G06F7/00

    CPC分类号： G06F7/762 ,  G06F5/015 ,  G06F7/768

    摘要： A circuit having a single branch, which is controllable to implement either a left or right shift of bits of a data word. Preferably, the circuit is controllable to implement any selected one of the following operations: a left or right shift of bits of the word; and rotation (to the left or right) of bits of the word. In a preferred implementation, the circuit includes a set of multiplexer stages and circuitry for selectively inverting the order of the bits of the word input to, and the word output from, the set of multiplexer stages. Each of the multiplexer stages shifts the bits of the word it receives either by zero bits (in response to a first control signal), or by a positive number of bits (in response to a second control signal). By selectively controlling various subsets of the multiplexer stages, the bits of the input word can be shifted by any of a number of places (from zero to N, where N is some positive number). In another aspect, the invention is a circuit for rotating bits of an input word (by two or more bits to the left or right) during a single cycle, by duplicating the input word to form an extended word, shifting bits of the extended word, and selecting a subset of the shifted bits of the extended word. Other aspects of the invention are methods performed by, and a digital signal processor including, either embodiment of the inventive circuit.

    摘要翻译： 具有单个分支的电路，其可控制以实现数据字的位的左移或右移。 优选地，电路是可控制的，以实现以下操作中的任何选择的一个：字的位的左移或右移; 以及字的位的旋转（向左或向右）。 在优选的实施方案中，电路包括一组多路复用器级和电路，用于选择性地反转字输入的位的顺序和多路复用器级的集合输出的字。 多路复用器级中的每一个通过零位（响应于第一控制信号）或通过正数位（响应于第二控制信号）来移位其接收的字的位。 通过选择性地控制多路复用器级的各个子集，可以通过多个位置（从零到N，其中N是一些正数）中的任意一个来移位输入字的位。 另一方面，本发明是一种电路，用于在单个周期期间通过复制输入字以形成扩展字来转换输入字的位（向左或向右两位或更多位），从而使扩展字的位移位 ，并且选择扩展字的移位位的子集。 本发明的其他方面是由本发明的电路的任一实施例执行的方法和数字信号处理器。

    Method for approximating and optimizing gains in capacity and coverage resulting from deployment of multi-antennas in cellular radio networks
    5.
    发明授权
    Method for approximating and optimizing gains in capacity and coverage resulting from deployment of multi-antennas in cellular radio networks 有权
    用于近似和优化在蜂窝无线电网络中部署多天线所产生的容量和覆盖增益的方法

    公开(公告)号：US08428171B2

    公开(公告)日：2013-04-23

    申请号：US12724746

    申请日：2010-03-16

    申请人： Gerhard Fettweis ,  Jens Voigt ,  Joerg Schueler

    发明人： Gerhard Fettweis ,  Jens Voigt ,  Joerg Schueler

    IPC分类号： H04B7/02 ,  H04L1/02

    CPC分类号： H01Q1/246 ,  H01Q25/00 ,  H04B7/0413 ,  H04B7/10 ,  H04B17/391 ,  H04W16/00 ,  H04W84/042

    摘要： A method is provided for planning and optimizing the configuration of a radio access network which comprises base stations and receivers and employs a mobile radio technology that allows and/or enforces use of multi-antenna types at said base stations and receivers. By a ray tracing algorithm which is performed between said transmitter positions and said receiver positions using a 3D clutter height matrix, a scalar metric is determined for each receiver position which directly reflects a capacity gain resulting from applying a multi-antenna type instead of a single antenna at said transmitter and receiver positions. This scalar metric allows in an algorithmically advantageous way to analyze the relative performance of different MIMO antenna types in a potential deployment area and to select and deploy an optimal MIMO antenna type for a particular coverage sector.

    摘要翻译： 提供了一种用于规划和优化包括基站和接收机的无线电接入网络的配置的方法，并采用允许和/或强制在所述基站和接收机处使用多天线类型的移动无线电技术。 通过使用3D杂波高度矩阵在所述发射器位置和所述接收器位置之间执行的光线跟踪算法，针对直接反映由应用多天线类型而不是单个天线类型而产生的容量增益的每个接收器位置确定标量度量 在所述发射机和接收机位置的天线。 该标量度量允许以算法有利的方式分析潜在部署区域中不同MIMO天线类型的相对性能，并为特定覆盖区域选择和部署最佳MIMO天线类型。

    Processor bus arrangement
    7.
    发明申请
    Processor bus arrangement 有权
    处理器总线布置

    公开(公告)号：US20050216640A1

    公开(公告)日：2005-09-29

    申请号：US10381216

    申请日：2001-09-21

    申请人： Wolfram Drescher ,  Gerhard Fettweis

    发明人： Wolfram Drescher ,  Gerhard Fettweis

    IPC分类号： G06F13/36 ,  G06F13/40

    CPC分类号： G06F13/4022

    摘要： A processor bus arrangement including several data processing units, each connected to a line system specified as a bus. The bus includes connection units and bus segments, where the bus segments are connected to the bus in a seperable manner through the connection units. This guarantees that the functional units, arranged on the bus, carry out the information thereof, by means of the bus and may carry out an exchange independently of other functional units. Furthermore, other functional units in different groups may carry out an information exchange simultaneously, by means of the bus. As the connection units perform the function of the defined combinatory connection of the signal lines, the bus segments generate the physical connections between the connection units. This ensures that the connection units carry out the information exchange with as many connected functional units as required. The information path from a functional unit can be switched by toggling to selected functional units by simultaneous connection to several functional units or by bridging non-participating functional units. One method of switching the circuitry of the connection unit is by using a multiplexer.

    摘要翻译： 一种处理器总线布置，包括几个数据处理单元，每个数据处理单元连接到指定为总线的线路系统。 总线包括连接单元和总线段，其中总线段通过连接单元以可分离的方式连接到总线。 这保证了布置在总线上的功能单元通过总线执行其信息，并且可以独立于其他功能单元执行交换。 此外，不同组中的其他功能单元可以通过总线同时进行信息交换。 当连接单元执行信号线的定义的组合连接的功能时，总线段产生连接单元之间的物理连接。 这确保连接单元与所需的连接功能单元进行信息交换。 可以通过同时连接到多个功能单元或通过桥接非参与功能单元来切换到功能单元的信息路径。 切换连接单元的电路的一种方法是使用多路复用器。

    Data calculating device and method for processing data in data block form
    8.
    发明授权
    Data calculating device and method for processing data in data block form 有权
    用于以数据块形式处理数据的数据计算装置和方法

    公开(公告)号：US06728739B1

    公开(公告)日：2004-04-27

    申请号：US09719351

    申请日：2000-12-12

    申请人： Shiro Kobayashi ,  Gerhard Fettweis

    发明人： Shiro Kobayashi ,  Gerhard Fettweis

    IPC分类号： G06F501

    CPC分类号： G06F7/483 ,  G06F7/485 ,  G06F7/49936 ,  G06F7/509

    摘要： A data calculating device preferably used to improve the calculation precision when fixed-point calculation is performed by block-floating-point system. Each piece of data of a data group is calculated, the minimum scale factor representative of the calculated data is detected as a group scale factor (GSF), and calculated data is subjected to scaling based on the detected GSFs. These processing are applied to each data group of a data block. The minimum GSF out of the detected GSFs is detected as a block scale factor (BSF). When calculation of the calculated data is performed again, the calculated data of the data group is subjected to scaling according to the GSFs and BSF before the calculation performed again.

    摘要翻译： 一种数据计算装置，优选地用于在通过块浮点系统执行定点计算时提高计算精度。计算数据组的每条数据，表示计算数据的最小比例因子被检测为 组比例因子（GSF）和计算数据根据检测到的GSF进行缩放。 这些处理被应用于数据块的每个数据组。 检测到的GSF中的最小GSF被检测为块比例因子（BSF）。 当再次执行计算的数据的计算时，在再次执行计算之前，根据GSF和BSF对计算出的数据组的数据进行缩放。

    Procedure and processor arrangement for parallel data processing
    9.
    发明授权
    Procedure and processor arrangement for parallel data processing 失效
    并行数据处理的程序和处理器布置

    公开(公告)号：US06618800B1

    公开(公告)日：2003-09-09

    申请号：US09484776

    申请日：2000-01-18

    申请人： Matthias Weiss ,  Gerhard Fettweis

    发明人： Matthias Weiss ,  Gerhard Fettweis

    IPC分类号： G06F1300

    CPC分类号： G06F13/1663

    摘要： A procedure and a processor arrangement for parallel data processing in which data are read out from a data memory and are conveyed via a communications unit to processing units for parallel processing. The data are divided into data groups with several elements and are stored in a group memory under a common address. To each data group, a processing unit is allocated, in that at least one element of a data group can be directly linked to the allocated processing unit, directly bypassing the communications unit. In a parallel fashion, a data group is read out from the data memory and is distributed over one or several processing units and is processed in a parallel fashion in the latter.

    摘要翻译： 一种用于并行数据处理的过程和处理器装置，其中从数据存储器读出数据并经由通信单元传送到用于并行处理的处理单元。 数据被分成具有多个元素的数据组，并且以公共地址存储在组存储器中。 对于每个数据组，分配处理单元，其中数据组的至少一个元素可以直接链接到分配的处理单元，直接绕过通信单元。 以并行方式，从数据存储器读出数据组，并且分布在一个或多个处理单元上，并在后者中以并行方式处理数据组。