利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

27 条记录 (耗时 0.023 秒)

    Method for forming semiconductor memory capacitor without cell-to-cell bridges
    3.
    发明授权
    Method for forming semiconductor memory capacitor without cell-to-cell bridges 失效
    用于形成半导体存储器电容器而不使用电池到电池桥的方法

    公开(公告)号：US07498267B2

    公开(公告)日：2009-03-03

    申请号：US11776750

    申请日：2007-07-12

    申请人： Gyu Hyun Kim ,  Yong Soo Choi

    发明人： Gyu Hyun Kim ,  Yong Soo Choi

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L28/91 ,  H01L27/10852 ,  Y10S438/905

    摘要： A capacitor is formed by forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate. A metal storage node is formed on the surface of each of the storage node holes in the mold insulating layer. The mold insulating layer is removed by performing the following steps: loading the semiconductor substrate with the storage node in the chamber for in-situ cleaning, rinsing, and drying processes; removing the mold insulating layer by an etchant in the chamber; then rinsing the semiconductor substrate by introducing deionized water into the chamber while discharging the etchant out of the chamber; finally rinsing the rinsed semiconductor substrate with a mixed solution of the deionized water and organic solvent; drying the finally rinsed semiconductor substrate by IPA vapor in the chamber while discharging the mixed solution of the deionized water and organic solvent out of the chamber.

    摘要翻译： 通过在半导体衬底上形成具有多个存储节点孔的模具绝缘层来形成电容器。 金属存储节点形成在模具绝缘层中的每个存储节点孔的表面上。 通过执行以下步骤去除模具绝缘层：将具有存储节点的半导体衬底装载在用于原位清洁，漂洗和干燥过程的室中; 通过腔室中的蚀刻剂去除模具绝缘层; 然后通过将去离子水引入室中来冲洗半导体衬底，同时将蚀刻剂排出室; 最后用去离子水和有机溶剂的混合溶液冲洗冲洗的半导体衬底; 在室内通过IPA蒸气干燥最终漂洗的半导体衬底，同时将去离子水和有机溶剂的混合溶液排出室外。

    METHOD FOR FORMING SEMICONDUCTOR MEMORY CAPACITOR WITHOUT CELL-TO-CELL BRIDGES
    4.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR MEMORY CAPACITOR WITHOUT CELL-TO-CELL BRIDGES 失效
    无细胞桥形成半导体存储器电容器的方法

    公开(公告)号：US20080102594A1

    公开(公告)日：2008-05-01

    申请号：US11776750

    申请日：2007-07-12

    申请人： Gyu Hyun KIM ,  Yong Soo CHOI

    发明人： Gyu Hyun KIM ,  Yong Soo CHOI

    IPC分类号： H01L21/306

    CPC分类号： H01L28/91 ,  H01L27/10852 ,  Y10S438/905

    摘要： A capacitor is formed by forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate. A metal storage node is formed on the surface of each of the storage node holes in the mold insulating layer. The mold insulating layer is removed by performing the following steps: loading the semiconductor substrate with the storage node in the chamber for in-situ cleaning, rinsing, and drying processes; removing the mold insulating layer by an etchant in the chamber; then rinsing the semiconductor substrate by introducing deionized water into the chamber while discharging the etchant out of the chamber; finally rinsing the rinsed semiconductor substrate with a mixed solution of the deionized water and organic solvent; drying the finally rinsed semiconductor substrate by IPA vapor in the chamber while discharging the mixed solution of the deionized water and organic solvent out of the chamber.

    摘要翻译： 通过在半导体衬底上形成具有多个存储节点孔的模具绝缘层来形成电容器。 金属存储节点形成在模具绝缘层中的每个存储节点孔的表面上。 通过执行以下步骤去除模具绝缘层：将具有存储节点的半导体衬底装载在用于原位清洁，漂洗和干燥过程的室中; 通过腔室中的蚀刻剂去除模具绝缘层; 然后通过将去离子水引入室中来冲洗半导体衬底，同时将蚀刻剂排出室; 最后用去离子水和有机溶剂的混合溶液冲洗冲洗的半导体衬底; 在室内通过IPA蒸气干燥最终漂洗的半导体衬底，同时将去离子水和有机溶剂的混合溶液排出室外。

    Method for forming capacitor of semiconductor device
    7.
    发明授权
    Method for forming capacitor of semiconductor device 有权
    形成半导体器件电容器的方法

    公开(公告)号：US07846809B2

    公开(公告)日：2010-12-07

    申请号：US11965901

    申请日：2007-12-28

    申请人： Gyu Hyun Kim

    发明人： Gyu Hyun Kim

    IPC分类号： H01L21/20 ,  H01L21/8242

    CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L28/91

    摘要： A method for forming a capacitor of a semiconductor device includes the steps of forming first and second sacrificial insulation layers over a semiconductor substrate divided into first and second regions. The second and first sacrificial insulation layers in the first region are etched to define in the first region of the semiconductor substrate. Storage nodes on surfaces of the holes are formed. A partial thickness of the second sacrificial insulation layer is etched to partially expose upper portions of the storage nodes. A mask pattern is formed to cover the first region while exposing the second sacrificial insulation layer remaining in the second region. The exposed second sacrificial insulation layer in the second region is removed to expose the first sacrificial insulation layer in the second region. The exposed first sacrificial insulation layer in the second region and the first sacrificial insulation layer in the first region is removed. The mask pattern is removed. The second sacrificial insulation layer remaining in the first region is removed.

    摘要翻译： 一种形成半导体器件的电容器的方法包括以下步骤：在分成第一和第二区域的半导体衬底上形成第一和第二牺牲绝缘层。 蚀刻第一区域中的第二和第一牺牲绝缘层以限定在半导体衬底的第一区域中。 形成孔的表面上的存储节点。 蚀刻第二牺牲绝缘层的部分厚度以部分地暴露存储节点的上部。 形成掩模图案以覆盖第一区域，同时暴露残留在第二区域中的第二牺牲绝缘层。 去除第二区域中暴露的第二牺牲绝缘层，以露出第二区域中的第一牺牲绝缘层。 在第二区域中暴露的第一牺牲绝缘层和第一区域中的第一牺牲绝缘层被去除。 去除掩模图案。 残留在第一区域中的第二牺牲绝缘层被去除。

    METHOD FOR CHEMICAL MECHANICAL POLISHING IN A SCAN MANNER OF A SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHOD FOR CHEMICAL MECHANICAL POLISHING IN A SCAN MANNER OF A SEMICONDUCTOR DEVICE 审中-公开
    半导体器件扫描仪中的化学机械抛光方法

    公开(公告)号：US20080261399A1

    公开(公告)日：2008-10-23

    申请号：US11946110

    申请日：2007-11-28

    申请人： Yong Soo Choi ,  Gyu Hyun Kim

    发明人： Yong Soo Choi ,  Gyu Hyun Kim

    IPC分类号： H01L21/302

    CPC分类号： H01L21/02074 ,  H01L21/67028

    摘要： The chemical mechanical polishing of a semiconductor device includes polishing a target layer to be polished through a chemical reaction by slurry and a mechanical process by a polishing pad. Then performing a post cleaning composed of cleaning, rinsing and drying of the surface of the polished target layer. The parts for cleaning, rinsing and drying procedures are arranged in a row and the post cleaning is performed in a scan manner using a bar type module. Provided at the cleaning and rinsing parts, a solution supplying nozzle and a retrieving nozzle disposed at both sides of the solution supplying nozzle. Finally, removing the solution supplied to the target layer to be polished immediately after the solution comes in contact with the target layer.

    摘要翻译： 半导体器件的化学机械抛光包括通过浆料的化学反应和通过抛光垫的机械过程抛光待抛光的目标层。 然后进行由抛光对象层的表面的清洗，冲洗和干燥构成的后清洗。 用于清洁，冲洗和干燥过程的部件被排列成一排，并且使用条形模块以扫描方式执行后清洗。 在清洁和漂洗部分设置有溶液供应喷嘴和设置在溶液供应喷嘴两侧的回收喷嘴。 最后，在溶液与目标层接触之后，立即将提供给目标层的溶液移除。

    Multi-threshold CMOS latch circuit
    9.
    发明授权
    Multi-threshold CMOS latch circuit 失效
    多阈值CMOS锁存电路

    公开(公告)号：US07391249B2

    公开(公告)日：2008-06-24

    申请号：US11607743

    申请日：2006-12-01

    申请人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    发明人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    IPC分类号： H03K3/289

    CPC分类号： H03K3/356156 ,  H03K3/012

    摘要： Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

    摘要翻译： 提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。