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    Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices
    1.
    发明授权
    Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices 失效
    设计半导体器件的方法和修改半导体器件布局的方法

    公开(公告)号：US08621399B2

    公开(公告)日：2013-12-31

    申请号：US13458516

    申请日：2012-04-27

    申请人： Kyung-Tae Do ,  Yong-Seok Lee ,  Hyo-Sig Won ,  Jung-Yun Choi ,  Jong-Ho Kim

    发明人： Kyung-Tae Do ,  Yong-Seok Lee ,  Hyo-Sig Won ,  Jung-Yun Choi ,  Jong-Ho Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.

    摘要翻译： 在设计半导体器件的方法中，可以选择包括在半导体器件的布局中的晶体管。 可以设置偏置数据以改变所选择的晶体管的特性。 可以在忽略偏置数据之后执行用于半导体器件的布局的设计规则检查（DRC）处理。 可以基于偏置数据执行用于半导体器件的布局的光学邻近校正（OPC）处理。

    POWER CONTROL CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME
    2.
    发明申请
    POWER CONTROL CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
    功率控制电路，包括其的半导体器件

    公开(公告)号：US20130069690A1

    公开(公告)日：2013-03-21

    申请号：US13603878

    申请日：2012-09-05

    申请人： Hyung Ock KIM ,  Jae Han JEON ,  Jung Yun CHOI ,  Hyo Sig WON ,  Kyu Myung CHOI

    发明人： Hyung Ock KIM ,  Jae Han JEON ,  Jung Yun CHOI ,  Hyo Sig WON ,  Kyu Myung CHOI

    IPC分类号： H03K17/16

    CPC分类号： H03K19/0016 ,  H03K19/00361 ,  Y10T307/461 ,  Y10T307/951

    摘要： A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.

    摘要翻译： 功率控制电路连接在电源电压和逻辑电路之间，以切换提供给逻辑电路的电力。 功率控制电路包括并联接收外部模式改变信号的多个第一功率门控单元（PGC），与一个第一PGC连接的至少一个第二PGC，与至少一个第二PGC连接的至少一个第三PGC，以及 与所述至少一个第三PGC连接的至少一个第四PGC。 第二电源门控单元，第三PGC和/或第四PGC可以包括多个门控单元。 第二，第三和第四多个中的至少一个具有串联连接的电力门控单元。 第一至第四PGC中的每一个响应于模式改变信号而切换供电。

    Method of estimating a leakage current in a semiconductor device
    4.
    发明授权
    Method of estimating a leakage current in a semiconductor device 有权
    估计半导体器件中漏电流的方法

    公开(公告)号：US08156460B2

    公开(公告)日：2012-04-10

    申请号：US12547729

    申请日：2009-08-26

    申请人： Kyung-Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    发明人： Kyung-Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： In a method of estimating a leakage current in a semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of a cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function of a segment is generated by arithmetically operating the virtual cell leakage characteristic functions of all cells in the segment. Then, a full chip leakage characteristic function of the chip is generated by statistically operating the segment leakage characteristic functions of all segments in the chip. Accordingly, computational loads of Wilkinson's method for generating the full chip leakage characteristic function can remarkably be reduced.

    摘要翻译： 在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。 空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。 通过算术运算实际泄漏特性函数产生单元的虚拟单元泄漏特性函数。 通过对片段中所有单元的虚拟单元泄漏特性函数进行算术运算，产生段的段泄漏特性函数。 然后，通过统计操作芯片中所有段的段泄漏特性函数来产生芯片的全芯片泄漏特性功能。 因此，Wilkinson用于产生全芯片泄漏特性功能的方法的计算负载可以显着降低。

    Method of Estimating a Leakage Current in a Semiconductor Device
    5.
    发明申请
    Method of Estimating a Leakage Current in a Semiconductor Device 有权
    估算半导体器件中泄漏电流的方法

    公开(公告)号：US20100058258A1

    公开(公告)日：2010-03-04

    申请号：US12547729

    申请日：2009-08-26

    申请人： Kyung Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    发明人： Kyung Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of the cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function is generated by arithmetically operating the virtual cell leakage characteristic functions of each cell in the segment. Then, a full chip leakage characteristic function is generated by statistically operating the segment leakage characteristic functions of each segment in the chip. Accordingly, the computational loads of Wilkinson's method for generating the full chip leakage characteristic function may be remarkably reduced.

    摘要翻译： 在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。 空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。 通过算术运算实际漏电特性函数产生单元的虚拟单元泄漏特性函数。 通过对片段中每个单元的虚拟单元泄漏特性函数进行算术运算来产生段泄漏特性函数。 然后，通过统计操作芯片中每个段的段泄漏特性函数来产生全片泄漏特性函数。 因此，威尔金森的用于产生全芯片泄漏特性函数的方法的计算量可以显着降低。

    Body biasing control circuit using lookup table and body biasing control method using same
    6.
    发明授权
    Body biasing control circuit using lookup table and body biasing control method using same 有权
    使用查找表和身体偏置控制方法使用本体偏置控制电路

    公开(公告)号：US07616048B2

    公开(公告)日：2009-11-10

    申请号：US11849486

    申请日：2007-09-04

    申请人： Byunghee Choi ,  Jun Seomun ,  Jung-yun Choi ,  Hyo-sig Won ,  Youngsoo Shin

    发明人： Byunghee Choi ,  Jun Seomun ,  Jung-yun Choi ,  Hyo-sig Won ,  Youngsoo Shin

    IPC分类号： H03K3/01

    CPC分类号： H03K19/00384 ,  G05F3/205 ,  H03K2217/0018

    摘要： A body biasing control circuit capable of being shared by a plurality of macro blocks and can independently control body voltages of a plurality of macro blocks. The body biasing control circuit includes a lookup table for storing a plurality of indexes where each index is associated with a body voltage appropriate for an operating state of a corresponding macro block. A control unit receives a corresponding index from the lookup table and generates a plurality of body voltages appropriate for an operating state of a macro block corresponding to the index and supplies the body voltages to the macro block.

    摘要翻译： 一种能够被多个宏块共享的主体偏置控制电路，并且可以独立地控制多个宏块的体电压。 身体偏置控制电路包括用于存储多个索引的查找表，其中每个索引与适于相应的宏块的操作状态的体电压相关联。 控制单元从查找表接收相应的索引，并产生适合于与索引相对应的宏块的操作状态的多个体电压，并将体电压提供给宏块。

    METHOD OF DESIGNING A SEMICONDUCTOR DEVICE
    7.
    发明申请
    METHOD OF DESIGNING A SEMICONDUCTOR DEVICE 失效
    设计半导体器件的方法

    公开(公告)号：US20120297349A1

    公开(公告)日：2012-11-22

    申请号：US13458516

    申请日：2012-04-27

    申请人： Kyung-Tae Do ,  Yong-Seok Lee ,  Hyo-Sig Won ,  Jung-Yun Choi ,  Jong-Ho Kim

    发明人： Kyung-Tae Do ,  Yong-Seok Lee ,  Hyo-Sig Won ,  Jung-Yun Choi ,  Jong-Ho Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.

    摘要翻译： 在设计半导体器件的方法中，可以选择包括在半导体器件的布局中的晶体管。 可以设置偏置数据以改变所选择的晶体管的特性。 可以在忽略偏置数据之后执行用于半导体器件的布局的设计规则检查（DRC）处理。 可以基于偏置数据执行用于半导体器件的布局的光学邻近校正（OPC）处理。

    Control circuits and methods including delay times for multi-threshold CMOS devices
    8.
    发明授权
    Control circuits and methods including delay times for multi-threshold CMOS devices 有权
    控制电路和方法包括多阈值CMOS器件的延迟时间

    公开(公告)号：US07215155B2

    公开(公告)日：2007-05-08

    申请号：US10996084

    申请日：2004-11-23

    申请人： Hyo-sig Won

    发明人： Hyo-sig Won

    IPC分类号： H03K19/096 ,  H03K3/037

    CPC分类号： H03K19/0963 ,  H03K19/0016

    摘要： Multi-Threshold CMOS (MTCMOS) devices include a high threshold voltage current control switch that is responsive to a first control signal, a low threshold voltage logic circuit and a flip-flop that is configured to store data from the low threshold voltage logic circuit and that is responsive to a second control signal. A control circuit also is provided that is configured to change a logic state of the second control signal and then, after a first delay, to change a logic state of the first control signal, in response to the MTCMOS device entering a sleep mode. The control circuit is further configured to change the logic state of the first control signal and then, after a second delay that is different from the first delay, to change the logic state of the second control signal in response to the MTCMOS device entering an active mode. Related methods also are provided.

    摘要翻译： 多阈值CMOS（MTCMOS）器件包括响应于第一控制信号的高阈值电压电流控制开关，低阈值电压逻辑电路和触发器，其被配置为存储来自低阈值电压逻辑电路的数据， 其响应于第二控制信号。 还提供了一种控制电路，其被配置为响应于MTCMOS设备进入休眠模式而改变第二控制信号的逻辑状态，然后在第一延迟之后改变第一控制信号的逻辑状态。 控制电路还被配置为改变第一控制信号的逻辑状态，然后在与第一延迟不同的第二延迟之后，响应于MTCMOS设备进入活动状态来改变第二控制信号的逻辑状态 模式。 还提供了相关方法。

    Clocked-scan flip-flop for multi-threshold voltage CMOS circuit
    10.
    发明授权
    Clocked-scan flip-flop for multi-threshold voltage CMOS circuit 失效
    用于多阈值电压CMOS电路的时钟扫描触发器

    公开(公告)号：US06861887B2

    公开(公告)日：2005-03-01

    申请号：US10330427

    申请日：2002-12-30

    申请人： Kwang-ok Jeong ,  Hyo-sig Won

    发明人： Kwang-ok Jeong ,  Hyo-sig Won

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  H01L21/822 ,  H01L27/04 ,  H03K3/012 ,  H03K3/037 ,  H03K3/289

    CPC分类号： G01R31/318541 ,  H03K3/012

    摘要： A clocked-scan flip-flop for multi-threshold CMOS (MTCMOS) is provided. The clocked-scan flip-flop includes a first switching unit which switches normal data that are input from the outside and outputs the data; a second switching unit which switches scan data that are input from the outside and outputs the data; a latch unit which latches the data input from the first switching unit or the second switching unit; and a clock input unit which controls the switching operations of the first and second switching units according to the result of a predetermined operation on a clock signal and a scan clock signal that are input from the outside. The clocked-scan flip-flop has the characteristics of a complementary pass-transistor (CP) flip-flop, that is, low power consumption and high performance. Also, the clocked-scan flip-flop provides a full-scale scan function for test purposes.

    摘要翻译： 提供了多阈值CMOS（MTCMOS）的时钟扫描触发器。 时钟扫描触发器包括：第一切换单元，其切换从外部输入的正常数据并输出数据; 第二切换单元，切换从外部输入的扫描数据，并输出该数据; 锁存单元，其锁存从第一切换单元或第二切换单元输入的数据; 以及时钟输入单元，其根据对从外部输入的时钟信号和扫描时钟信号的预定操作的结果来控制第一和第二开关单元的切换操作。 时钟扫描触发器具有互补的通过晶体管（CP）触发器的特性，即低功耗和高性能。 此外，时钟扫描触发器为测试目的提供全尺寸扫描功能。