公开(公告)号：US07689941B1

公开(公告)日：2010-03-30

申请号：US11803091

申请日：2007-05-11

申请人： Teng Chow Ooi ,  Yanzhong Xu ,  Jeffrey T. Watt ,  Haiming Yu

发明人： Teng Chow Ooi ,  Yanzhong Xu ,  Jeffrey T. Watt ,  Haiming Yu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.

摘要翻译： 提供了用于计算双端口存储器的写入边距的系统和方法。 使用电路设计工具生成双端口存储器阵列单元的设计。 用户修改双端口存储器阵列单元的设计以并入两个电压源。 电压源用于表示存储单元上的差分噪声。 写余量计算工具使用电路仿真工具对修改后的双端口存储器阵列单元进行写入读取操作的瞬态仿真。 在瞬态模拟期间，电压源上的电压电平有系统地变化。 通过分析用于电压源的每个电压电平的瞬态模拟结果来确定双端口存储器的写入裕度。

公开(公告)号：US08643108B2

公开(公告)日：2014-02-04

申请号：US13214102

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Yanzhong Xu ,  Lin-Shih Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Yanzhong Xu ,  Lin-Shih Liu

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L21/761 ,  H01L29/66795

摘要： One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及缓冲晶体管器件。 该器件包括形成在半导体衬底中的缓冲的垂直鳍状结构。 垂直鳍状结构至少包括上半导体层，缓冲区和阱区​​的至少一部分。 缓冲区具有第一掺杂极性，并且阱区具有与第一掺杂极性相反的第二掺杂极性。 在缓冲区和阱区​​之间形成至少部分覆盖垂直鳍状结构的水平横截面的至少一个p-n结。 还公开了其它实施例，方面和特征。

公开(公告)号：US08519403B1

公开(公告)日：2013-08-27

申请号：US12931584

申请日：2011-02-04

申请人： Che Ta Hsu ,  Christopher J. Pass ,  Dale Ibbotson ,  Jeffrey T. Watt ,  Yanzhong Xu

发明人： Che Ta Hsu ,  Christopher J. Pass ,  Dale Ibbotson ,  Jeffrey T. Watt ,  Yanzhong Xu

IPC分类号： H01L27/108 ,  H01L29/00 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L21/823807 ,  H01L21/26586 ,  H01L29/1083

摘要： A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.

摘要翻译： 一种形成亚微米器件的方法包括在包括第一掺杂剂型的多晶硅阱和第二掺杂剂型的栅极的第一区域和包括第二掺杂剂型多晶硅阱的第二区域的第一区域上沉积硬掩模， 第一掺杂剂类型的栅极。 第一个区域上的硬掩模被去除。 执行第一掺杂剂类型的倾斜植入以在第二掺杂剂类型的栅极下形成凹穴。

公开(公告)号：US08482963B1

公开(公告)日：2013-07-09

申请号：US12629831

申请日：2009-12-02

申请人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

发明人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

公开(公告)号：US08705300B1

公开(公告)日：2014-04-22

申请号：US12850528

申请日：2010-08-04

申请人： Yanzhong Xu ,  Jeffrey T. Watt

发明人： Yanzhong Xu ,  Jeffrey T. Watt

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/08 ,  G11C5/147 ,  G11C11/417 ,  G11C29/021 ,  G11C29/028

摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays with memory cells arranged in rows and columns. Address lines may be associated with each row of memory cells and data lines may be associated with each column of memory cells. Precharge driver circuitry may be used to precharge the data lines to a precharge voltage prior to performing read operations. The integrated circuit may contain core logic that is powered using a core logic power supply voltage. The precharge voltage may be reduced with respect to the core logic power supply voltage. Each address transistor may have a body bias terminal. The integrated circuit may contain programmable voltage regulator circuitry that produces a body bias for the address transistors based on a body bias setting stored in nonvolatile memory on the integrated circuit.

摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有存储器阵列，存储器单元以行和列排列。 地址线可以与每行存储器单元相关联，并且数据线可以与每列存储器单元相关联。 预充电驱动器电路可以用于在执行读取操作之前将数据线预充电到预充电电压。 集成电路可能包含使用核心逻辑电源电压供电的核心逻辑。 可以相对于核心逻辑电源电压来减小预充电电压。 每个地址晶体管可以具有体偏置端子。 集成电路可以包含可编程电压调节器电路，其基于存储在集成电路中的非易失性存储器中的体偏置设置而产生用于地址晶体管的体偏置。

公开(公告)号：US08630113B1

公开(公告)日：2014-01-14

申请号：US12277411

申请日：2008-11-25

申请人： Yanzhong Xu ,  Jeffrey T. Watt

发明人： Yanzhong Xu ,  Jeffrey T. Watt

IPC分类号： G11C11/34

CPC分类号： G11C11/34

摘要： An integrated circuit (IC) includes a memory circuit. The memory circuit includes a plurality of thyristors. The plurality of thyristors are coupled in tandem.

摘要翻译： 集成电路（IC）包括存储电路。 存储电路包括多个晶闸管。 多个晶闸管串联耦合。

公开(公告)号：US08611137B2

公开(公告)日：2013-12-17

申请号：US13304226

申请日：2011-11-23

申请人： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

发明人： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

IPC分类号： G11C11/00

CPC分类号： G11C11/52 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  H01H1/0094 ,  H01H1/20 ,  H01H59/0009 ,  H01L27/101 ,  H01L27/11

摘要： Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.

摘要翻译： 提供具有存储元件的集成电路。 集成电路可以包括形成在具有互补金属氧化物半导体（CMOS）器件的第一部分中的逻辑电路，并且可以包括形成在具有纳米机电（NEM）器件的第二部分中的存储器元件和相关联的存储器电路的至少一部分， 中继设备 NEM和CMOS器件可以通过介电堆叠中的通孔互连。 第一和第二部分中的装置可以接收相应的电源电压。 在一个合适的布置中，存储器元件可以包括提供非易失性存储特性和软错误失真（SEU）抗扰性的两个继电器开关。 在另一种合适的布置中，存储元件可以包括第一和第二交叉耦合反相电路。 第一反相电路可以包括继电器开关，而第二反相电路仅包括CMOS晶体管。 以这种方式配置的存储器元件可用于提供易失性存储特性和SEU抗扰度。

公开(公告)号：US08355292B2

公开(公告)日：2013-01-15

申请号：US12571143

申请日：2009-09-30

申请人： Yanzhong Xu ,  Jeffrey T. Watt

发明人： Yanzhong Xu ,  Jeffrey T. Watt

IPC分类号： G11C5/14

CPC分类号： G11C11/4125 ,  H03K19/0033

摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.

摘要翻译： 提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。 存储元件可以各自具有十个晶体管。 为了克服将数据写入存储元件的困难，可以调整提供给阵列的一个或多个信号的信号强度。 在为每个存储元件供电时使用两个正电源电压。 电源电压之一可能相对于另一个电源电压暂时降低，以增强数据加载操作期间的写入裕度。 可以以这种方式调整的其他信号强度包括其他电源信号，数据信号电平，地址和清除信号幅度以及接地信号强度。 可调电源电路和数据读写控制电路可用于进行这些信号强度的调整。

公开(公告)号：US08077500B2

公开(公告)日：2011-12-13

申请号：US12820410

申请日：2010-06-22

申请人： Yanzhong Xu ,  Jeffrey T. Watt

发明人： Yanzhong Xu ,  Jeffrey T. Watt

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C11/4125 ,  H03K19/0033

摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.

摘要翻译： 提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。 存储元件可以各自具有十个晶体管。 为了克服将数据写入存储元件的困难，可以调整提供给阵列的一个或多个信号的信号强度。 在为每个存储元件供电时使用两个正电源电压。 电源电压之一可能相对于另一个电源电压暂时降低，以增强数据加载操作期间的写入裕度。 可以以这种方式调整的其他信号强度包括其他电源信号，数据信号电平，地址和清除信号幅度以及接地信号强度。 可调电源电路和数据读写控制电路可用于进行这些信号强度的调整。

公开(公告)号：US20100254203A1

公开(公告)日：2010-10-07

申请号：US12820410

申请日：2010-06-22

申请人： Yanzhong Xu ,  Jeffrey T. Watt

发明人： Yanzhong Xu ,  Jeffrey T. Watt

IPC分类号： G11C7/00

CPC分类号： G11C11/4125 ,  H03K19/0033

摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.