公开(公告)号：US20160163690A1

公开(公告)日：2016-06-09

申请号：US14809299

申请日：2015-07-27

申请人： Jae-Hyok Ko ,  Han-Gu Kim ,  Han-Gu Kim ,  Jong-Kyu Song ,  Jin Heo

发明人： Jae-Hyok Ko ,  Han-Gu Kim ,  Han-Gu Kim ,  Jong-Kyu Song ,  Jin Heo

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/36 ,  H01L29/10

CPC分类号： H01L27/0262 ,  H01L27/027

摘要： In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

摘要翻译： 在ESD保护装置中，第一导电类型的第一阱和第二导电类型的第二阱形成在基板中以彼此接触。 第一导电类型的第一杂质区和第二导电类型的第二杂质区形成在第一阱中，并且电连接到第一电极焊盘。 第二杂质区域在第二阱的方向上与第一杂质区间隔开。 在第二阱中形成第三杂质区，具有第二导电类型，并且电连接到第二电极焊盘。 在第二阱中形成第四杂质区，位于第一阱的从第三杂质区方向接触第三杂质区，具有第一导电类型，并且是电漂浮的。

公开(公告)号：US07898034B2

公开(公告)日：2011-03-01

申请号：US12292026

申请日：2008-11-10

申请人： Ki-Tae Lee ,  Han-Gu Kim ,  Jae-Hyok Ko

发明人： Ki-Tae Lee ,  Han-Gu Kim ,  Jae-Hyok Ko

IPC分类号： H01L23/62

CPC分类号： H01L23/60 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.

摘要翻译： 半导体芯片可以包括布置在至少第一和第二行中的多个焊盘以及连接到多个焊盘的多个保护电路。 多个保护电路可以包括至少一个二极管。 第一保护电路可以连接到第一排焊盘中的第一焊盘，并且第二保护电路可以连接到第二排焊盘中的第二焊盘。 第一和第二保护电路可以布置在第一排焊盘的下方。

公开(公告)号：US20070176241A1

公开(公告)日：2007-08-02

申请号：US11654638

申请日：2007-01-18

申请人： Ki-Tae Lee ,  Han-Gu Kim ,  Jae-Hyok Ko

发明人： Ki-Tae Lee ,  Han-Gu Kim ,  Jae-Hyok Ko

IPC分类号： H01L23/62

CPC分类号： H01L23/60 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.

摘要翻译： 半导体芯片可以包括布置在至少第一和第二行中的多个焊盘以及连接到多个焊盘的多个保护电路。 多个保护电路可以包括至少一个二极管。 第一保护电路可以连接到第一排焊盘中的第一焊盘，并且第二保护电路可以连接到第二排焊盘中的第二焊盘。 第一和第二保护电路可以布置在第一排焊盘的下方。

公开(公告)号：US20060124994A1

公开(公告)日：2006-06-15

申请号：US11265583

申请日：2005-11-02

申请人： Sung-Pil Jang ,  Han-Gu Kim ,  Chan-Hee Jeon

发明人： Sung-Pil Jang ,  Han-Gu Kim ,  Chan-Hee Jeon

IPC分类号： H01L29/76

CPC分类号： H01L29/7809 ,  H01L29/42368 ,  H01L29/7805

摘要： The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of a second conductivity type. Another source region is a second diffusion structure in which a heavily doped diffusion layer of a first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in the body region of the second conductivity type. An impurity diffusion structure of the source region in close proximity to the drain region is changed to be operated as a diode, thereby forming a strong current path to ESD (Electro-Static Discharge) or EOS (Electrical Over Stress). As a result, it is possible to prevent the device from being broken down.

摘要翻译： 本文公开的本发明是包含反向二极管的垂直双扩散金属氧化物半导体（VDMOS）器件。 该器件包括从漏极区域隔离的多个源极区域。 靠近漏极区域的源极区域是第一扩散结构，其中在第二导电类型的体区域中形成第二导电类型的重掺杂扩散层。 另一个源区是第二扩散结构，其中在第二导电类型的体区中形成第一导电类型的重掺杂扩散层和第二导电类型的重掺杂扩散层。 改变靠近漏极区的源极区的杂质扩散结构作为二极管工作，从而形成ESD（静电放电）或EOS（电过压）的强电流路径。 结果，可以防止装置分解。

公开(公告)号：US09620502B2

公开(公告)日：2017-04-11

申请号：US14178480

申请日：2014-02-12

申请人： Chan-Hee Jeon ,  Eun-Kyoung Kwon ,  Il-Ryong Kim ,  Han-Gu Kim ,  Woo-Jin Seo ,  Ki-Tae Lee

发明人： Chan-Hee Jeon ,  Eun-Kyoung Kwon ,  Il-Ryong Kim ,  Han-Gu Kim ,  Woo-Jin Seo ,  Ki-Tae Lee

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L27/11

CPC分类号： H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0288 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

摘要： In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

公开(公告)号：US20110199346A1

公开(公告)日：2011-08-18

申请号：US13025754

申请日：2011-02-11

申请人： Jae Hyok Ko ,  Han Gu Kim ,  Chang Su Kim ,  Suk-Jin Kim ,  Kwan Young Kim

发明人： Jae Hyok Ko ,  Han Gu Kim ,  Chang Su Kim ,  Suk-Jin Kim ,  Kwan Young Kim

IPC分类号： G06F3/038 ,  H01L27/082 ,  H01L21/8222

CPC分类号： H01L21/761 ,  H01L27/0251

摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type, at least two first well regions which have a second conductivity type and a predetermined depth in the semiconductor substrate, at least one second well region which has the first conductivity type and a predetermined depth in each of the first well regions, and a guard-ring region which has the second conductivity type and a predetermined depth and is positioned between the first well regions to be separated by a predetermined distance from the first well regions. The guard-ring region is connected to a ground voltage.

摘要翻译： 半导体器件包括具有第一导电类型的半导体衬底，在半导体衬底中具有第二导电类型和预定深度的至少两个第一阱区，具有第一导电类型和预定深度的至少一个第二阱区 以及具有第二导电类型和预定深度并且位于第一阱区之间以与第一阱区隔开预定距离的保护环区域。 保护环区域连接到接地电压。

公开(公告)号：US07763941B2

公开(公告)日：2010-07-27

申请号：US11897435

申请日：2007-08-30

申请人： Han-gu Kim ,  Ki-tae Lee ,  Jae-hyok Ko ,  Woo-sub Kim ,  Sung-pil Jang

发明人： Han-gu Kim ,  Ki-tae Lee ,  Jae-hyok Ko ,  Woo-sub Kim ,  Sung-pil Jang

IPC分类号： H01L23/62

CPC分类号： H01L27/0251

摘要： There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VDD ESD protection element connected between an I/O pad and a VDD line, a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line, and a power clamp element connected between the VDD line and the VSS line, and wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.

摘要翻译： 提供了具有输入/输出静电放电（I / O ESD）保护单元的集成电路装置。 集成电路装置包括I / O ESD保护电池，其包括连接在I / O焊盘和VDD线之间的VDD ESD保护元件，连接在I / O焊盘和VSS线之间的接地电压（VSS）ESD保护元件 以及连接在VDD线和VSS线之间的电源钳位元件，其中I / O ESD保护单元中的VDD ESD保护元件，功率钳位元件和VSS ESD保护元件彼此相邻，因此它们 可以以直线连接或被布置为部分重叠。

公开(公告)号：US20080310061A1

公开(公告)日：2008-12-18

申请号：US12213231

申请日：2008-06-17

申请人： Chan-Hee Jeon ,  Kyoung-Sik Im ,  Hyun-Jun Choi ,  Han-Gu Kim

发明人： Chan-Hee Jeon ,  Kyoung-Sik Im ,  Hyun-Jun Choi ,  Han-Gu Kim

IPC分类号： H02H9/00 ,  H01L29/78

CPC分类号： H01L27/0285 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/4238 ,  H01L29/78

摘要： A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape.

摘要翻译： 具有电应力（EOS）保护的晶体管可以包括有源区，多个杂质区和导电图。 有源区可以形成在衬底中。 杂质区域可以形成在有源区域中并相对于彼此以预定或给定的距离布置。 导电图案可以以蜿蜒的形状布置在每个杂质区之间，并且导电图案可以包括连接到接地端子的中心部分。 因此，具有EOS保护的晶体管，钳位装置和包括该晶体管的ESD保护电路可以增加钳位装置的导通时间，并且可以通过包括配置有栅极的导电图案来充分地放电由于EOS引起的电荷， 以蜿蜒的形状相对于彼此连接。

公开(公告)号：US20080042206A1

公开(公告)日：2008-02-21

申请号：US11897435

申请日：2007-08-30

申请人： Han-gu Kim ,  Ki-tae Lee ,  Jae-hyok Ko ,  Woo-sub Kim ,  Sung-Pil Jang

发明人： Han-gu Kim ,  Ki-tae Lee ,  Jae-hyok Ko ,  Woo-sub Kim ,  Sung-Pil Jang

IPC分类号： H01L23/62 ,  H02H9/04

CPC分类号： H01L27/0251

摘要： There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VDD ESD protection element connected between an I/O pad and a VDD line, a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line, and a power clamp element connected between the VDD line and the VSS line, and wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.

摘要翻译： 提供了具有输入/输出静电放电（I / O ESD）保护单元的集成电路装置。 该集成电路装置包括I / O ESD保护单元，其包括连接在I / O焊盘和V DD线之间的V DDD ESD保护元件，接地电压（ 连接在I / O焊盘和V SS SS线之间的ESD保护元件，以及连接在V SUB端子之间的电源钳位元件 线和V SS线，并且其中V DD ESD保护元件，功率钳元件和V SS SS ESD保护元件在 I / O ESD保护单元彼此相邻，因此它们可以以直线连接或被布置成部分重叠。

公开(公告)号：US20070177329A1

公开(公告)日：2007-08-02

申请号：US11646535

申请日：2006-12-28

申请人： Kyoung-Sik Im ,  Han-Gu Kim ,  Jae-Hyok Ko ,  Il-Hun Son ,  Suk-Jin Kim

发明人： Kyoung-Sik Im ,  Han-Gu Kim ,  Jae-Hyok Ko ,  Il-Hun Son ,  Suk-Jin Kim

IPC分类号： H05F3/02

CPC分类号： H05K9/0067

摘要： A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.

摘要翻译： 提供了钳位电路，其可以通过使用已经包括在电路中的晶体管将电路节点处的电压钳位到稳定的电平。 当发生静电放电（ESD）时，钳位电路可以将半导体芯片内的电路的第一节点处的电压钳位到更稳定的水平。 钳位电路可以包括晶体管和电容元件，以存储控制电压以响应于ESD来导通晶体管。