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    Memory including error correction code circuit
    1.
    发明申请
    Memory including error correction code circuit 审中-公开
    存储器包括纠错码电路

    公开(公告)号：US20080168331A1

    公开(公告)日：2008-07-10

    申请号：US11650169

    申请日：2007-01-05

    申请人： Thomas Vogelsang ,  Harald Streif ,  Pete Chlumecky ,  Josef Schnell

    发明人： Thomas Vogelsang ,  Harald Streif ,  Pete Chlumecky ,  Josef Schnell

    IPC分类号： G11C29/00 ,  G06F11/07

    CPC分类号： G11C7/1006 ,  G06F11/1044 ,  G11C2029/0411

    摘要： A memory includes an array of memory cells and an error correction code circuit. The error correction code circuit is configured to receive a first portion of a first data word from an external circuit and a second portion of the first data word from the array of memory cells, combine the first portion and the second portion to provide the first data word, and encode the first data word for writing to the array of memory cells.

    摘要翻译： 存储器包括存储器单元阵列和纠错码电路。 误差校正码电路被配置为从存储器单元阵列的外部电路和第一数据字的第二部分接收第一数据字的第一部分，组合第一部分和第二部分以提供第一数据 字，并对第一数据字进行编码以写入存储器单元阵列。

    Memory with data clock receiver and command/address clock receiver
    2.
    发明申请
    Memory with data clock receiver and command/address clock receiver 审中-公开
    具有数据时钟接收器和命令/地址时钟接收器的存储器

    公开(公告)号：US20080137470A1

    公开(公告)日：2008-06-12

    申请号：US11635164

    申请日：2006-12-07

    申请人： Josef Schnell ,  Farrukh Aquil ,  Harald Streif

    发明人： Josef Schnell ,  Farrukh Aquil ,  Harald Streif

    IPC分类号： G11C8/00

    CPC分类号： G11C5/025 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076

    摘要： One embodiment provides a memory device including a memory bank, a first receiver, and a second receiver. The memory bank includes memory cells. The first receiver is configured to receive a clock signal and provide a data clock signal based on the clock signal. The second receiver is configured to receive the clock signal and provide a command/address clock signal based on the clock signal. The first receiver provides the data clock signal to output read data from the memory cells. The second receiver provides the command/address clock signal to execute commands.

    摘要翻译： 一个实施例提供了一种包括存储体，第一接收器和第二接收器的存储器件。 存储体包括存储单元。 第一接收器被配置为接收时钟信号并且基于时钟信号提供数据时钟信号。 第二接收器被配置为接收时钟信号并且基于时钟信号提供命令/地址时钟信号。 第一个接收器提供数据时钟信号以从存储器单元输出读取数据。 第二个接收器提供命令/地址时钟信号来执行命令。

    Method for controlling an electrical light source by pulse width modulation
    5.
    发明授权
    Method for controlling an electrical light source by pulse width modulation 有权
    通过脉宽调制控制电光源的方法

    公开(公告)号：US07888890B2

    公开(公告)日：2011-02-15

    申请号：US11661663

    申请日：2005-07-14

    申请人： Uli Joos ,  Christian Voss ,  Josef Schnell ,  Jochen Zwick

    发明人： Uli Joos ,  Christian Voss ,  Josef Schnell ,  Jochen Zwick

    IPC分类号： H05B41/36

    CPC分类号： H05B33/0851 ,  H05B33/0818 ,  H05B39/047 ,  Y02B20/346

    摘要： A method for controlling electrical light sources, in particular, light-emitting diodes (LEDs) by pulse width modulation of a supply voltage is disclosed, whereby the supply voltage or a parameter dependent thereon, for example the current or the electrical power, is measured and the pulse width is controlled as a function thereof. According to the invention, for the light source a characteristic curve for the brightness is generated as a function of the supply voltage or the parameter dependent thereon and, from the measured supply voltage or the parameter dependent thereon, an actual brightness value is determined with the characteristic curve and is compared with a given brightness value and the pulse width controlled as a function thereof.

    摘要翻译： 公开了一种通过电源电压的脉冲宽度调制来控制电光源，特别是发光二极管（LED）的方法，由此测量电源电压或其所依赖的参数，例如电流或电功率 并且作为其功能控制脉冲宽度。 根据本发明，对于光源，根据供电电压或依赖于其的参数产生亮度的特性曲线，并且根据所测量的电源电压或依赖于其的参数，实际亮度值由 特性曲线，并与给定的亮度值进行比较，其脉冲宽度作为其功能受到控制。

    Memory with clock distribution options
    9.
    发明申请
    Memory with clock distribution options 审中-公开
    内存带时钟分配选项

    公开(公告)号：US20080137471A1

    公开(公告)日：2008-06-12

    申请号：US11635189

    申请日：2006-12-07

    申请人： Josef Schnell ,  Farrukh Aquil

    发明人： Josef Schnell ,  Farrukh Aquil

    IPC分类号： G11C7/22

    CPC分类号： G11C7/1078 ,  G06F1/10 ,  G11C5/063 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4093

    摘要： One embodiment provides a memory including a first receiver, a second receiver, a circuit, a first buffer, and a second buffer. The first receiver is situated on one side of the memory and configured to receive a first clock signal and provide a first clock tree signal. The second receiver is situated on another side of the memory and configured to receive a second clock signal and provide a second clock tree signal. The circuit is configured to receive the first clock tree signal and provide a distributed clock signal. The first buffer is configured to selectively provide one of the first clock tree signal and the distributed clock signal to the one side of the memory and the second buffer is configured to selectively provide one of the second clock tree signal and the distributed clock signal to the other side of the memory.

    摘要翻译： 一个实施例提供了包括第一接收器，第二接收器，电路，第一缓冲器和第二缓冲器的存储器。 第一接收器位于存储器的一侧，并被配置为接收第一时钟信号并提供第一时钟树信号。 第二接收器位于存储器的另一侧，并被配置为接收第二时钟信号并提供第二时钟树信号。 电路被配置为接收第一时钟树信号并提供分布式时钟信号。 第一缓冲器被配置为选择性地将第一时钟树信号和分布式时钟信号之一提供给存储器的一侧，并且第二缓冲器被配置为选择性地将第二时钟树信号和分布式时钟信号中的一个提供给 记忆的另一面。

    Boosted clock circuit for semiconductor memory
    10.
    发明授权
    Boosted clock circuit for semiconductor memory 有权
    用于半导体存储器的升压时钟电路

    公开(公告)号：US07376042B2

    公开(公告)日：2008-05-20

    申请号：US11492636

    申请日：2006-07-25

    申请人： Josef Schnell ,  Helmut Seitz

    发明人： Josef Schnell ,  Helmut Seitz

    IPC分类号： G11C8/00 ,  G11C5/14 ,  G11C7/00

    CPC分类号： G11C7/1072 ,  G11C7/222

    摘要： A memory component includes at least one memory bank array, a DQ region, a clock tree, and a voltage generator. The memory component is configured in a semiconductor wafer. The at least one memory bank array is configured such that data is read out of it during a read operation. The clock tree is coupled to the DQ region and is configured for driving data during the read operation. The voltage generator is coupled to at least some components of the clock tree in order to provide at least some of the components of the clock tree with an increased voltage.

    摘要翻译： 存储器组件包括至少一个存储体阵列，DQ区，时钟树和电压发生器。 存储器部件配置在半导体晶片中。 至少一个存储体阵列被配置为使得在读取操作期间从其读出数据。 时钟树耦合到DQ区，并且被配置为在读取操作期间驱动数据。 电压发生器耦合到时钟树的至少一些组件，以便提供时钟树的至少一些组件具有增加的电压。