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    POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    3.
    发明申请
    POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 失效
    功率半导体器件及其制造方法

    公开(公告)号：US20130069173A1

    公开(公告)日：2013-03-21

    申请号：US13592560

    申请日：2012-08-23

    Applicant: Woo Jin CHANG ,  Jong Won LIM ,  Ho Kyun AHN ,  Sang Choon KO ,  Sung Bum BAE ,  Chull Won JU ,  Young Rak PARK ,  Jae Kyoung MUN ,  Eun Soo NAM

    Inventor： Woo Jin CHANG ,  Jong Won LIM ,  Ho Kyun AHN ,  Sang Choon KO ,  Sung Bum BAE ,  Chull Won JU ,  Young Rak PARK ,  Jae Kyoung MUN ,  Eun Soo NAM

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66901 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

    Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode;and a metal configured to connect the field plate and the source electrode.

    Abstract translation: 公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。 根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。

    Power semiconductor device and fabrication method thereof
    4.
    发明授权
    Power semiconductor device and fabrication method thereof 失效
    功率半导体器件及其制造方法

    公开(公告)号：US08772833B2

    公开(公告)日：2014-07-08

    申请号：US13592560

    申请日：2012-08-23

    Applicant: Woo Jin Chang ,  Jong Won Lim ,  Ho Kyun Ahn ,  Sang Choon Ko ,  Sung Bum Bae ,  Chull Won Ju ,  Young Rak Park ,  Jae Kyoung Mun ,  Eun Soo Nam

    Inventor： Woo Jin Chang ,  Jong Won Lim ,  Ho Kyun Ahn ,  Sang Choon Ko ,  Sung Bum Bae ,  Chull Won Ju ,  Young Rak Park ,  Jae Kyoung Mun ,  Eun Soo Nam

    IPC: H01L29/15

    CPC classification number: H01L29/66901 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

    Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

    Abstract translation: 公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。 根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。

    FIELD EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF
    5.
    发明申请
    FIELD EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF 审中-公开
    场效应晶体管及其制造方法

    公开(公告)号：US20130069127A1

    公开(公告)日：2013-03-21

    申请号：US13556377

    申请日：2012-07-24

    Applicant: Ho Kyun AHN ,  Jong-Won Lim ,  Sung Bum Bae ,  Sang Choon Ko ,  Young Rak Park ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Eun Soo Nam ,  Jeong Jin Kim ,  Chull Won Ju

    Inventor： Ho Kyun AHN ,  Jong-Won Lim ,  Sung Bum Bae ,  Sang Choon Ko ,  Young Rak Park ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Eun Soo Nam ,  Jeong Jin Kim ,  Chull Won Ju

    IPC: H01L29/78 ,  H01L21/20

    CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/8128

    Abstract: A method for fabricating a field effect transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a cap layer, an ohmic metal layer and an insulating layer on a substrate; forming multilayered photoresists on the insulating layer; patterning the multilayered photoresists to form a photoresist pattern including a first opening for gate electrode and a second opening for field electrode; etching the insulating layer by using the photoresist pattern as an etching mask so that the insulating layer in the first opening is etched more deeply and the cap layer is exposed through the first opening; etching the cap layer exposed by etching the insulating layer through the first opening to form a gate recess region; and depositing a metal on the gate recess region and the etched insulating layer to form a gate-field electrode layer.

    Abstract translation: 根据本公开的示例性实施例的制造场效应晶体管的方法包括：在衬底上形成有源层，覆盖层，欧姆金属层和绝缘层; 在所述绝缘层上形成多层光致抗蚀剂; 图案化多层光致抗蚀剂以形成包括用于栅电极的第一开口和场电极的第二开口的光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻绝缘层，使得第一开口中的绝缘层被更深地蚀刻并且盖层通过第一开口暴露; 通过蚀刻绝缘层通过第一开口蚀刻暴露的盖层，以形成栅极凹陷区域; 以及在所述栅极凹部区域和所述蚀刻绝缘层上沉积金属以形成栅极电极层。

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