摘要:
Some microprocessors check branch prediction information in a branch history table and/or a branch target buffer. To check for branch prediction information, a microprocessor can identify which instructions are control flow instructions and which instructions are non control flow instructions. To reduce power consumption in the branch history table and/or branch target buffer, the branch history table and/or branch target buffer can check for branch prediction information corresponding to the control flow instructions and not the non control flow instructions.
摘要:
In a network-on-chip (NoC) system, multiple data messages may be transferred among modules of the system. Power consumption due to the transfer of the messages may affect a cost and overall performance of the system. A described technique provides a way to reduce a volume of data transferred in the NoC system by exploiting redundancy of data messages. Thus, if a data message to be sent from a source in the NoC includes so-called “zero” bytes that are bytes including only bits set to “0,” such zero bytes may not be transmitted in the NoC. Information on whether each byte of the data message is a zero byte may be recorded in a storage such as a data structure. This information, together with non-zero bytes of the data message, may form a compressed version of the data message. The information may then be used to uncompress the compressed data message at a destination.
摘要:
A handheld drain clearing device includes a first compressed air collection chamber and a cylindrical chamber for housing a cylinder. The central axis of said cylindrical chamber coincides with the central axis of said first compressed air collection chamber. A second compressed air collection chamber is formed within said cylindrical chamber and extends into said first compressed air collection chamber. To operate, a user first pushes the air into the second compressed air collection chamber, and then further pushes said cylinder inward to force said compressed air through a gate, into the first compressed air collection chamber. Finally, use a trigger component to discharge the highly compressed air to clear the blockage.
摘要:
Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.
摘要:
A method comprises storing data relating to the wear of a component of at least one turbine system in a database of a system for processing wear related information, generating a displayable menu containing a plurality of user-selectable links respectively associated with software modules of the system, and receiving an on-line selection of one of the user-selectable links to enable the associated software module of the system to generate displayable content including information relating to the wear of the component of the turbine system. The selected module may enable a quantitative amount of the wear of the component or qualitative wear range characterizing the amount of the wear of the component to be input and received on-line. Alternatively, the selected module may enable a component type to be input and received on-line and display a component fleet leader.
摘要:
Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.
摘要:
A technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. In an embodiment, each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.
摘要:
A comparison circuit can reduce the amount of power consumed when searching a load queue or a store queue of a microprocessor. Some embodiments of the comparison circuit use a comparison unit that performs an initial comparison of addresses using a subset of the address bits. If the initial comparison results in a match, a second comparison unit can be enabled to compare another subset of the address bits.
摘要:
An embodiment comprises includes an apparatus with a housing wearable by a subject and a first sensor operable to detect a position of the subject. An embodiment of the apparatus includes a second sensor operable to detect a body state of the subject, where the first body state may be a vital sign such as heart rate, blood pressure, body temperature or respiratory rate. The apparatus may also include a wireless module, and be operable to transmit body state data and position data to a remote device. The apparatus may include a gyroscope or an accelerometer, and may be operable to detect rotational change in the subject's position about and axis, linear acceleration of the subject along an axis, a change in position of the subject, or a rate of change in position of the subject.
摘要:
An embodiment comprises and apparatus having an image capture device with an image axis and a gyroscope operable to indicate the orientation of the image axis. An embodiment of a capsule endoscopy system comprises an imaging capsule and an external unit. The imaging capsule may comprise an image capture device having an image axis and a gyroscope operable to indicate the orientation of the image axis. The external unit may comprise a gyroscope operable to indicate an orientation of a subject and a harness wearable by a subject and operable to align the gyroscope with the subject. The imaging capsule may send and image to an external unit for processing and display, and the external unit may provide for calculation of the image-axis orientation relative to the body.