公开(公告)号：US20130161786A1

公开(公告)日：2013-06-27

申请号：US13333564

申请日：2011-12-21

申请人： Jen Jui Huang ,  Che Chi Lee ,  Shih Shu Tsai ,  Cheng Shun Chen ,  Shao Ta Hsu ,  Chao Wen Lay ,  Chun I. Hsieh ,  Ching Kai Lin

发明人： Jen Jui Huang ,  Che Chi Lee ,  Shih Shu Tsai ,  Cheng Shun Chen ,  Shao Ta Hsu ,  Chao Wen Lay ,  Chun I. Hsieh ,  Ching Kai Lin

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L27/10817 ,  H01L27/105 ,  H01L27/10852 ,  H01L28/91

摘要： A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.

摘要翻译： 电容器阵列包括多个电容器和支撑框架。 每个电容器包括电极。 支撑框架支撑多个电极，并且包括对应于多个电极的多个支撑结构。 每个支撑结构可以围绕相应的电极。 支撑框架可以包括掺杂可氧化材料的氧化物。

公开(公告)号：US20120149172A1

公开(公告)日：2012-06-14

申请号：US12962655

申请日：2010-12-08

申请人： Jen-Jui Huang ,  Hung-Ming Tsai

发明人： Jen-Jui Huang ,  Hung-Ming Tsai

IPC分类号： H01L21/31

CPC分类号： H01L21/76227

摘要： A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench.

摘要翻译： 描述了一种用于制造沟槽隔离结构的方法。 在衬底中形成沟槽。 至少在沟槽中形成衬垫层。 至少在沟槽的侧壁上形成前体层。 前体层被转换成具有比前体层更大的体积并填充沟槽的绝缘层。

公开(公告)号：US07713855B2

公开(公告)日：2010-05-11

申请号：US11780484

申请日：2007-07-20

申请人： Yu-Chung Fang ,  Hong-Wen Lee ,  Kuo-Chung Chen ,  Jen-Jui Huang ,  Jing-Kae Liou

发明人： Yu-Chung Fang ,  Hong-Wen Lee ,  Kuo-Chung Chen ,  Jen-Jui Huang ,  Jing-Kae Liou

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76895 ,  H01L27/10888

摘要： A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.

摘要翻译： 一种用于形成位线接触插塞的方法包括：提供包括晶体管的衬底，所述晶体管在栅极结构的两侧包括栅极结构和源极/漏极; 形成导电层，位线接触材料层和硬掩模层; 执行使用导电层作为蚀刻停止层的蚀刻工艺，以蚀刻位线接触材料层和硬掩模层，并在源极/漏极上形成位线接触插塞。 晶体管结构包括在栅极结构的两侧处的栅极结构和源极/漏极，覆盖栅极结构的一部分并连接到源极/漏极的导电层，以及布置在导电层上的位线接触插塞， 直接连接到导电层。

公开(公告)号：US20090087978A1

公开(公告)日：2009-04-02

申请号：US11958974

申请日：2007-12-18

申请人： Chao-Wen Lay ,  Jen-Jui Huang

发明人： Chao-Wen Lay ,  Jen-Jui Huang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76831

摘要： An interconnect process is provided. A substrate is provided. A plurality of gate structures is disposed on the substrate, and doped regions are disposed in the substrate and respectively located between two adjacent gate structure. A liner is conformally formed above the substrate. A dielectric layer is formed above the substrate. A contact opening is formed in the dielectric layer between two neighboring gate structures to expose the liner on the doped region and on a portion of the top surface and a portion of the sidewall of each of the gate structures. A polymer material is deposited on the liner on the portion of the top surface of each of the gate structures and on the doped region. The liner on the doped regions is removed. A conductive layer is filled in the contact opening, which is free of electrical connection to the gate structures.

摘要翻译： 提供互连过程。 提供基板。 多个栅极结构设置在衬底上，并且掺杂区域设置在衬底中并分别位于两个相邻栅极结构之间。 衬垫保形地形成在衬底之上。 在衬底上形成介电层。 在两个相邻栅极结构之间的电介质层中形成接触开口以暴露掺杂区域上的衬垫以及每个栅极结构的顶表面的一部分和侧壁的一部分。 聚合物材料沉积在每个栅极结构的顶表面的部分上和衬底上的掺杂区上。 去除掺杂区域上的衬垫。 导电层填充在接触开口中，该接触开口不与门结构电连接。

公开(公告)号：US20080286935A1

公开(公告)日：2008-11-20

申请号：US11969913

申请日：2008-01-06

申请人： Jen-Jui Huang ,  Hsiu-Chun Lee ,  Chang-Ho Yeh

发明人： Jen-Jui Huang ,  Hsiu-Chun Lee ,  Chang-Ho Yeh

IPC分类号： H01L21/76

CPC分类号： H01L21/763 ,  H01L21/76232 ,  H01L27/1087

摘要： A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench.

摘要翻译： 制造隔离浅沟槽的方法包括：提供具有至少深沟槽的衬底，在深沟槽的上部形成覆盖层，在覆盖层的一部分上形成外壳层，限定延伸穿过该沟槽的沟槽 盖层和导电层，并在浅沟槽中形成隔离层。

公开(公告)号：US20080254589A1

公开(公告)日：2008-10-16

申请号：US11829067

申请日：2007-07-26

申请人： Jen-Jui Huang ,  Chih-Ching Lin

发明人： Jen-Jui Huang ,  Chih-Ching Lin

IPC分类号： H01L21/20

CPC分类号： H01L29/66181 ,  H01L27/1087

摘要： A method for manufacturing collars of deep trench capacitors includes providing a substrate with a deep trench in which there is a trench capacitor in the bottom; forming an inner wall layer completely covering the deep trench and the substrate; forming a hard mask layer on the surface of the inner wall layer; performing a selective implanting but not on the hard mask layer on the wall of the deep trench; performing a selective wet etching to remove the not implanted hard mask layer; and performing an anisotropic dry etching to substantially remove the inner wall layer on the bottom of the deep trench so as to partially expose the trench capacitor and to substantially retain the collars of the deep trench capacitors intact.

摘要翻译： 一种用于制造深沟槽电容器的套环的方法包括：向衬底提供深沟槽，其中在底部存在沟槽电容器; 形成完全覆盖深沟槽和衬底的内壁层; 在内壁层的表面上形成硬掩模层; 执行选择性植入，但不在深沟槽的壁上的硬掩模层上进行; 执行选择性湿蚀刻以去除未注入的硬掩模层; 并进行各向异性干蚀刻以基本上去除深沟槽底部的内壁层，以便部分地暴露沟槽电容器并且基本上保持深沟槽电容器的套环完好无损。

公开(公告)号：US20130299884A1

公开(公告)日：2013-11-14

申请号：US13468797

申请日：2012-05-10

申请人： Shian Jyh Lin ,  Jen Jui Huang

发明人： Shian Jyh Lin ,  Jen Jui Huang

IPC分类号： H01L29/772 ,  H01L21/02

CPC分类号： H01L21/76224 ,  H01L27/10876 ,  H01L27/10891

摘要： A memory device includes a substrate, first and second trench isolations, a plurality of line-type isolations, a first word line, and a second word line. The substrate comprises an active area having source and drain regions. The first and second trench isolations extend parallel to each other. The line-type isolations define the active area together with the first and second trench isolations. The first word line extends across the active area and is formed in the substrate adjacent to the first trench isolation defining a first segment of the active area with the first trench isolation. The second word line extends across the active area and is formed in the substrate adjacent to the second trench isolation defining a second segment of the active area with the second trench isolation. The size of the first segment is substantially equal to the size of the second segment.

摘要翻译： 存储器件包括衬底，第一和第二沟槽隔离，多个线型隔离，第一字线和第二字线。 衬底包括具有源区和漏区的有源区。 第一和第二沟槽隔离物彼此平行延伸。 线型隔离定义了有源区以及第一和第二沟槽隔离。 第一字线延伸穿过有效区域，并且形成在邻近第一沟槽隔离物的衬底中，限定具有第一沟槽隔离的有源区域的第一段。 第二字线延伸穿过有效区域并且形成在与第二沟槽隔离件相邻的衬底中，限定具有第二沟槽隔离的有源区域的第二段。 第一段的大小基本上等于第二段的大小。

公开(公告)号：US20090124079A1

公开(公告)日：2009-05-14

申请号：US12042347

申请日：2008-03-05

申请人： Jen-Jui Huang ,  Chih-Ching Lin ,  Kuo-Chung Chen

发明人： Jen-Jui Huang ,  Chih-Ching Lin ,  Kuo-Chung Chen

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L27/10888

摘要： A method for fabricating a conductive plug includes the steps of providing a substrate having at least a gate structure thereon, a first dielectric layer covering a surface of the substrate, a second dielectric layer disposed on the first dielectric layer, and at least a metal line formed within the second dielectric layer; forming a hard mask plug on the second dielectric layer; forming a third dielectric layer covering the second dielectric layer and the hard mask plug; removing a portion of the third dielectric layer to expose the hard mask plug; removing the hard mask plug to form a plug hole; and forming the conductive plug within the plug hole to electrically connect with the gate structure.

摘要翻译： 一种用于制造导电插塞的方法包括以下步骤：提供其上具有至少栅极结构的衬底，覆盖衬底表面的第一介电层，设置在第一电介质层上的第二电介质层，以及至少金属线 形成在所述第二电介质层内; 在所述第二电介质层上形成硬掩模塞; 形成覆盖所述第二介电层和所述硬掩模塞的第三介电层; 去除所述第三电介质层的一部分以暴露所述硬掩模塞; 去除硬掩模塞以形成塞孔; 以及在所述插塞孔内形成所述导电插塞以与所述栅极结构电连接。

公开(公告)号：US07569451B2

公开(公告)日：2009-08-04

申请号：US11969913

申请日：2008-01-06

申请人： Jen-Jui Huang ,  Hsiu-Chun Lee ,  Chang-Ho Yeh

发明人： Jen-Jui Huang ,  Hsiu-Chun Lee ,  Chang-Ho Yeh

IPC分类号： H01L21/8242

CPC分类号： H01L21/763 ,  H01L21/76232 ,  H01L27/1087

摘要： A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench.

摘要翻译： 制造隔离浅沟槽的方法包括：提供具有至少深沟槽的衬底，在深沟槽的上部形成覆盖层，在覆盖层的一部分上形成外壳层，限定延伸穿过该沟槽的沟槽 盖层和导电层，并在浅沟槽中形成隔离层。

公开(公告)号：US20080303103A1

公开(公告)日：2008-12-11

申请号：US11932620

申请日：2007-10-31

申请人： Kuo Chung CHEN ,  Jen-Jui HUANG ,  Hong Wen LEE

发明人： Kuo Chung CHEN ,  Jen-Jui HUANG ,  Hong Wen LEE

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L21/26586 ,  H01L21/28061 ,  H01L29/1037 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/66613

摘要： The present invention provides a semiconductor structure and a method of forming the same. The method includes the steps of providing a substrate, forming a mask layer with an opening on the substrate, locally oxidizing the substrate to form an oxide layer within the opening, removing the oxide layer, such that a partial surface of the substrate becomes a curve surface, forming a sacrificial layer on the curve surface, forming a first doped region in the substrate and under the hard mask layer, forming a gate stack within the opening, removing the hard mask layer, forming a spacer on a sidewall of the gate stack, and forming a second doped region in the substrate and under the spacer. The second doped region has a dopant concentration is larger than that of the first doped region. Therefore, the oxide layer increases the surface area of the substrate so as to increase the channel length. Thus, the leakage between the source region and the drain region can be improved.

摘要翻译： 本发明提供一种半导体结构及其形成方法。 该方法包括以下步骤：提供衬底，在衬底上形成具有开口的掩模层，局部氧化衬底以在开口内形成氧化物层，去除氧化物层，使得衬底的部分表面变为曲线 在所述曲面上形成牺牲层，在所述衬底中并在所述硬掩模层之下形成第一掺杂区域，在所述开口内形成栅叠层，去除所述硬掩膜层，在所述栅叠层的侧壁上形成间隔物 并且在所述衬底中并在所述间隔物之下形成第二掺杂区域。 第二掺杂区域的掺杂浓度大于第一掺杂区域的掺杂浓度。 因此，氧化物层增加了衬底的表面积，从而增加了沟道长度。 因此，可以提高源极区域和漏极区域之间的泄漏。