公开(公告)号：US08981804B2

公开(公告)日：2015-03-17

申请号：US13530273

申请日：2012-06-22

申请人： Hun-Kyo Seo ,  Soon-Geol Hwang ,  Jang-Sun Kim

发明人： Hun-Kyo Seo ,  Soon-Geol Hwang ,  Jang-Sun Kim

IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R31/28

CPC分类号： G01R1/0466 ,  G01R31/2889

摘要： A contact apparatus includes a pusher having first and second surfaces, the first surface being connected to a pressure unit, stoppers protruding from edges of the second surface of the pusher away from the pressure unit, a pusher block having first and second surfaces facing each other, the first surface facing the pusher, and the second surface being connected to a semiconductor device, coupling members connecting the pusher to the pusher block, and a connector disposed between the pusher and the pusher block, at least part of a surface of the connector being circular, and the circular surface making a point contact with the pusher or the pusher block.

摘要翻译： 接触装置包括具有第一表面和第二表面的推动器，第一表面连接到压力单元，从推动器的第二表面的边缘突出的止动件远离压力单元;推动器块，其具有彼此面对的第一和第二表面 ，所述第一表面面向所述推动器，并且所述第二表面连接到半导体器件，将推动器连接到推动器块的联接构件以及设置在推动器和推动器块之间的连接器，连接器的至少一部分表面 圆形表面与推动器或推动块形成点接触。

公开(公告)号：US08407659B2

公开(公告)日：2013-03-26

申请号：US12829921

申请日：2010-07-02

申请人： Jae-Hoon Jeong ,  Chang-Woo Ko ,  Ki-Jae Song ,  Hun-Kyo Seo

发明人： Jae-Hoon Jeong ,  Chang-Woo Ko ,  Ki-Jae Song ,  Hun-Kyo Seo

IPC分类号： G06F17/50

CPC分类号： G01R1/0408 ,  G01R31/2808 ,  G06F17/5068 ,  G11C29/56 ,  G11C2029/5602

摘要： In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.

摘要翻译： 在设计印刷电路板的方法中，计算实际存储器件的封装电容，封装电感和芯片电容。 基于印刷电路板的特性来计算信号线的每单位长度的信号线电容和信号线电感。 基于封装电容和信号线电容确定每个引脚的信号线的长度。

公开(公告)号：US08106675B2

公开(公告)日：2012-01-31

申请号：US12458008

申请日：2009-06-29

申请人： Ki-Jae Song ,  Hun-Kyo Seo

发明人： Ki-Jae Song ,  Hun-Kyo Seo

IPC分类号： G01R31/02

CPC分类号： G11C29/56 ,  G01R31/31926 ,  G11C2029/2602 ,  G11C2029/5602

摘要： A test system may include a test device, a switching unit and/or a test board. The test device may be configured to generate a first test signal swinging between a first voltage level and a second voltage level, and the first voltage level may be lower than the second voltage level. The switching unit may be coupled to the test device, and configured to switch the first test signal to provide a second test signal swinging between a third voltage level and a fourth voltage level. The third voltage level may be lower than the fourth voltage level. A plurality of devices under test (DUTs) may be mounted on the test board. Each of the plurality of DUTs may be connected in parallel with respect to one another to the switching unit through a transmission line.

摘要翻译： 测试系统可以包括测试设备，开关单元和/或测试板。 测试装置可以被配置为产生在第一电压电平和第二电压电平之间摆动的第一测试信号，并且第一电压电平可以低于第二电压电平。 开关单元可以耦合到测试设备，并且被配置为切换第一测试信号以提供在第三电压电平和第四电压电平之间摆动的第二测试信号。 第三电压电平可能低于第四电压电平。 被测试的多个器件（DUT）可以安装在测试板上。 多个DUT中的每一个可以通过传输线相对于彼此并联连接到切换单元。

公开(公告)号：US20090322369A1

公开(公告)日：2009-12-31

申请号：US12458008

申请日：2009-06-29

申请人： Ki-Jae Song ,  Hun-Kyo Seo

发明人： Ki-Jae Song ,  Hun-Kyo Seo

IPC分类号： G01R31/02

CPC分类号： G11C29/56 ,  G01R31/31926 ,  G11C2029/2602 ,  G11C2029/5602

摘要： A test system may include a test device, a switching unit and/or a test board. The test device may be configured to generate a first test signal swinging between a first voltage level and a second voltage level, and the first voltage level may be lower than the second voltage level. The switching unit may be coupled to the test device, and configured to switch the first test signal to provide a second test signal swinging between a third voltage level and a fourth voltage level. The third voltage level may be lower than the fourth voltage level. A plurality of devices under test (DUTs) may be mounted on the test board. Each of the plurality of DUTs may be connected in parallel with respect to one another to the switching unit through a transmission line.

摘要翻译： 测试系统可以包括测试设备，开关单元和/或测试板。 测试装置可以被配置为产生在第一电压电平和第二电压电平之间摆动的第一测试信号，并且第一电压电平可以低于第二电压电平。 开关单元可以耦合到测试设备，并且被配置为切换第一测试信号以提供在第三电压电平和第四电压电平之间摆动的第二测试信号。 第三电压电平可能低于第四电压电平。 被测试的多个器件（DUT）可以安装在测试板上。 多个DUT中的每一个可以通过传输线相对于彼此并联连接到切换单元。

公开(公告)号：US08482308B2

公开(公告)日：2013-07-09

申请号：US12614504

申请日：2009-11-09

申请人： Ki-Jae Song ,  Hun-Kyo Seo ,  Jae-Il Lee ,  Jong-Won Han ,  Jong-Pil Park

发明人： Ki-Jae Song ,  Hun-Kyo Seo ,  Jae-Il Lee ,  Jong-Won Han ,  Jong-Pil Park

IPC分类号： G01R31/00 ,  G01R31/28

CPC分类号： G01R31/2886 ,  G01R1/0408

摘要： A connecting unit to test a semiconductor chip and an apparatus to test the semiconductor chip having the same include a plurality of connectors, on which a semiconductor chip having a certain pattern of electrical connection terminals, having a plurality of holes, cables configured to electrically connect the electrical connection terminals to the exterior, and coupling units configured to selectively electrically connect the cables to the electrical connection terminals through the holes. Therefore, it is possible to perform electrical tests of semiconductor chips having various patterns of electrical connection terminals and receive the semiconductor chips in a tray at a time.

摘要翻译： 用于测试半导体芯片的连接单元和用于测试具有该连接器的半导体芯片的装置包括多个连接器，其上具有一定形式的电连接端子的半导体芯片具有多个孔，电缆被配置为电连接 电连接端子到外部，以及耦合单元，其被配置成选择性地将电缆电连接到电连接端子上。 因此，可以对具有各种电连接端子的图案的半导体芯片进行电气测试，并且一次接收托盘中的半导体芯片。

公开(公告)号：US20130088250A1

公开(公告)日：2013-04-11

申请号：US13530273

申请日：2012-06-22

申请人： Hun-Kyo SEO ,  Soon-Geol Hwang ,  Jang-Sun Kim

发明人： Hun-Kyo SEO ,  Soon-Geol Hwang ,  Jang-Sun Kim

IPC分类号： G01R31/26 ,  G01R1/067

CPC分类号： G01R1/0466 ,  G01R31/2889

摘要： A contact apparatus includes a pusher having first and second surfaces, the first surface being connected to a pressure unit, stoppers protruding from edges of the second surface of the pusher away from the pressure unit, a pusher block having first and second surfaces facing each other, the first surface facing the pusher, and the second surface being connected to a semiconductor device, coupling members connecting the pusher to the pusher block, and a connector disposed between the pusher and the pusher block, at least part of a surface of the connector being circular, and the circular surface making a point contact with the pusher or the pusher block.

摘要翻译： 接触装置包括具有第一表面和第二表面的推动器，第一表面连接到压力单元，从推动器的第二表面的边缘突出的止动件远离压力单元;推动器块，其具有彼此面对的第一和第二表面 ，所述第一表面面向所述推动器，并且所述第二表面连接到半导体器件，将推动器连接到推动器块的联接构件以及设置在推动器和推动器块之间的连接器，连接器的至少一部分表面 圆形表面与推动器或推动块形成点接触。

公开(公告)号：US20110004861A1

公开(公告)日：2011-01-06

申请号：US12829921

申请日：2010-07-02

申请人： Jae-Hoon Jeong ,  Chang-Woo Ko ,  Ki-Jae Song ,  Hun-Kyo Seo

发明人： Jae-Hoon Jeong ,  Chang-Woo Ko ,  Ki-Jae Song ,  Hun-Kyo Seo

IPC分类号： G01R31/26 ,  G06F17/50

CPC分类号： G01R1/0408 ,  G01R31/2808 ,  G06F17/5068 ,  G11C29/56 ,  G11C2029/5602

摘要： In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.

摘要翻译： 在设计印刷电路板的方法中，计算实际存储器件的封装电容，封装电感和芯片电容。 基于印刷电路板的特性来计算信号线的每单位长度的信号线电容和信号线电感。 基于封装电容和信号线电容确定每个引脚的信号线的长度。

公开(公告)号：US20100117670A1

公开(公告)日：2010-05-13

申请号：US12614504

申请日：2009-11-09

申请人： Ki-jae SONG ,  Hun-Kyo SEO ,  Jae-Il LEE ,  Jong-Won HAN ,  Jong-Pil PARK

发明人： Ki-jae SONG ,  Hun-Kyo SEO ,  Jae-Il LEE ,  Jong-Won HAN ,  Jong-Pil PARK

IPC分类号： G01R31/02 ,  G01R31/26 ,  G01R1/06

CPC分类号： G01R31/2886 ,  G01R1/0408

摘要： A connecting unit to test a semiconductor chip and an apparatus to test the semiconductor chip having the same include a plurality of connectors, on which a semiconductor chip having a certain pattern of electrical connection terminals, having a plurality of holes, cables configured to electrically connect the electrical connection terminals to the exterior, and coupling units configured to selectively electrically connect the cables to the electrical connection terminals through the holes. Therefore, it is possible to perform electrical tests of semiconductor chips having various patterns of electrical connection terminals and receive the semiconductor chips in a tray at a time.

摘要翻译： 用于测试半导体芯片的连接单元和用于测试具有该连接器的半导体芯片的装置包括多个连接器，其上具有一定形式的电连接端子的半导体芯片具有多个孔，电缆被配置为电连接 电连接端子到外部，以及耦合单元，其被配置成选择性地将电缆电连接到电连接端子上。 因此，可以对具有各种电连接端子的图案的半导体芯片进行电气测试，并且一次接收托盘中的半导体芯片。

公开(公告)号：US08922233B2

公开(公告)日：2014-12-30

申请号：US13404244

申请日：2012-02-24

申请人： Hun-Kyo Seo

发明人： Hun-Kyo Seo

IPC分类号： G01R31/28

CPC分类号： G01R31/2894 ,  G01R31/2893

摘要： An apparatus for testing a semiconductor device includes a test socket, a test board, an ID reader, and an accumulator. The test socket comprises an ID information pattern and is configured to receive the semiconductor device. The test board is configured to detachably receive the test socket and electrically connect to the test socket. The ID reader is configured to read the ID information pattern and generate an ID signal corresponding to the test socket each time a semiconductor test is performed in the test socket. The accumulator is electrically connected to the ID reader and is configured to accumulate a plurality of ID signals, and store a test number equal to the number of times the test socket is used to perform the semiconductor test. The test number is based on the accumulated ID signals.

摘要翻译： 一种用于测试半导体器件的装置包括测试插座，测试板，ID读取器和累加器。 测试插座包括ID信息模式并被配置为接收半导体器件。 测试板被配置为可拆卸地接收测试插座并电连接到测试插座。 ID读取器被配置为每次在测试插座中执行半导体测试时读取ID信息模式并生成与测试插座对应的ID信号。 蓄电池电连接到ID读取器，并且被配置为累积多个ID信号，并且存储等于测试插座用于执行半导体测试的次数的测试号。 测试号码是基于积累的ID信号。

公开(公告)号：US20120229158A1

公开(公告)日：2012-09-13

申请号：US13404244

申请日：2012-02-24

申请人： Hun-Kyo SEO

发明人： Hun-Kyo SEO

IPC分类号： G01R31/26

CPC分类号： G01R31/2894 ,  G01R31/2893

摘要： An apparatus for testing a semiconductor device includes a test socket, a test board, an ID reader, and an accumulator. The test socket comprises an ID information pattern and is configured to receive the semiconductor device. The test board is configured to detachably receive the test socket and electrically connect to the test socket. The ID reader is configured to read the ID information pattern and generate an ID signal corresponding to the test socket each time a semiconductor test is performed in the test socket. The accumulator is electrically connected to the ID reader and is configured to accumulate a plurality of ID signals, and store a test number equal to the number of times the test socket is used to perform the semiconductor test. The test number is based on the accumulated ID signals.

摘要翻译： 一种用于测试半导体器件的装置包括测试插座，测试板，ID读取器和累加器。 测试插座包括ID信息模式并被配置为接收半导体器件。 测试板被配置为可拆卸地接收测试插座并电连接到测试插座。 ID读取器被配置为每次在测试插座中执行半导体测试时读取ID信息模式并生成与测试插座对应的ID信号。 蓄电池电连接到ID读取器，并且被配置为累积多个ID信号，并且存储等于测试插座用于执行半导体测试的次数的测试号。 测试号码是基于积累的ID信号。