中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.014 seconds)

    Memory device and method for verifying the same
    1.
    发明授权
    Memory device and method for verifying the same 有权
    用于验证其的存储器件和方法

    公开(公告)号：US09036424B2

    公开(公告)日：2015-05-19

    申请号：US13602952

    申请日：2012-09-04

    Applicant: Hyung-Min Lee

    Inventor： Hyung-Min Lee

    IPC: G11C11/34 ,  G11C16/34 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26

    CPC classification number: G11C16/3459 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26

    Abstract: A memory includes a cell string including a plurality of memory cells connected in series, a bit line connected to the cell string, a voltage transfer unit configured to electrically connect the bit line and a sensing node in response to a control signal, and a page buffer configured to sense a voltage of the bit line through the sensing node in a sensing period, wherein the page buffer decides a voltage level of the control signal based on a threshold voltage of the target memory cell, which corresponds to a verification target among the plurality of memory cells in the sensing period.

    Abstract translation: 存储器包括：单元串，包括串联连接的多个存储单元，连接到单元串的位线;电压转移单元，被配置为响应于控制信号电连接位线和感测节点;以及页面 缓冲器，其被配置为在感测周期中感测通过感测节点的位线的电压，其中，所述寻呼缓冲器基于所述目标存储器单元的阈值电压来决定所述控制信号的电压电平，所述阈值电压对应于所述目标存储器单元中的验证目标 在感测周期中的多个存储器单元。

    MEMORY DEVICE AND METHOD FOR VERIFYING THE SAME
    2.
    发明申请
    MEMORY DEVICE AND METHOD FOR VERIFYING THE SAME 有权
    存储装置及其验证方法

    公开(公告)号：US20130315003A1

    公开(公告)日：2013-11-28

    申请号：US13602952

    申请日：2012-09-04

    Applicant: Hyung-Min LEE

    Inventor： Hyung-Min LEE

    IPC: G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/3459 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26

    Abstract: A memory includes a cell string including a plurality of memory cells connected in series, a bit line connected to the cell string, a voltage transfer unit configured to electrically connect the bit line and a sensing node in response to a control signal, and a page buffer configured to sense a voltage of the bit line through the sensing node in a sensing period, wherein the page buffer decides a voltage level of the control signal based on a threshold voltage of the target memory cell, which corresponds to a verification target among the plurality of memory cells in the sensing period.

    Abstract translation: 存储器包括：单元串，包括串联连接的多个存储单元，连接到单元串的位线;电压转移单元，被配置为响应于控制信号电连接位线和感测节点;以及页面 缓冲器，其被配置为在感测周期中感测通过感测节点的位线的电压，其中，所述寻呼缓冲器基于所述目标存储器单元的阈值电压来决定所述控制信号的电压电平，所述阈值电压对应于所述目标存储器单元中的验证目标 在感测周期中的多个存储器单元。

    Digital-to-analog conversion circuit and column driver including the same
    4.
    发明授权
    Digital-to-analog conversion circuit and column driver including the same 有权
    数模转换电路和列驱动器包括相同

    公开(公告)号：US07948418B2

    公开(公告)日：2011-05-24

    申请号：US12630978

    申请日：2009-12-04

    Applicant: Gyu Hyeong Cho ,  Yoon Kyung Choi ,  Hyoung Rae Kim ,  Yong Joon Jeon ,  Hyung Min Lee ,  Sung Woo Lee

    Inventor： Gyu Hyeong Cho ,  Yoon Kyung Choi ,  Hyoung Rae Kim ,  Yong Joon Jeon ,  Hyung Min Lee ,  Sung Woo Lee

    IPC: H03M1/66

    CPC classification number: H03M1/664 ,  G09G3/20 ,  G09G2310/027 ,  G09G2310/0272 ,  G09G2310/0291 ,  H03M1/662 ,  H03M1/68

    Abstract: A digital-to-analog conversion circuit includes a digital-to-analog converter and a buffer amplifier. The digital-to-analog converter receives upper bits of digital data and a plurality of analog voltages and is configured to output two adjacent analog voltages of the plurality of analog voltages based on the upper bits. The buffer amplifier includes two input terminals. One of the input terminals receives one of the two adjacent analog voltages and the other input terminal receives the other adjacent analog voltage. The buffer amplifier is configured to generate a current offset by controlling a current flowing into each of the two input terminals based on lower bits of the digital bits.

    Abstract translation: 数模转换电路包括数模转换器和缓冲放大器。 数模转换器接收高位数字数据和多个模拟电压，并且被配置为基于高位输出多个模拟电压的两个相邻的模拟电压。 缓冲放大器包括两个输入端。 一个输入端子接收两个相邻的模拟电压中的一个，另一个输入端子接收另一个相邻的模拟电压。 缓冲放大器被配置为通过基于数字位的较低位来控制流入两个输入端中的每一个的电流来产生电流偏移。

    NONVOLATILE MEMORY DEVICE
    5.
    发明申请
    NONVOLATILE MEMORY DEVICE 有权
    非易失性存储器件

    公开(公告)号：US20130083596A1

    公开(公告)日：2013-04-04

    申请号：US13337200

    申请日：2011-12-26

    Applicant: Hyung-Min LEE

    Inventor： Hyung-Min LEE

    IPC: G11C16/10

    CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

    Abstract: Embodiments of present invention relate to a nonvolatile memory device that includes a first page buffer controlling any one of a first even bit line and a first odd bit line; a second page buffer controlling any one of a second even bit line and a second odd bit line; wherein the second page buffer operates the second odd bit line according to program when the first page buffer operates the first even bit line according to program, and the second page buffer operates the second even bit line according to program when the first page buffer operates the first odd bit line according to program.

    Abstract translation: 本发明的实施例涉及一种非易失性存储器件，其包括控制第一偶数位线和第一奇数位线中的任何一个的第一页缓冲器; 第二页缓冲器，其控制第二偶数位线和第二奇数位线中的任何一个; 其中当第一页缓冲器根据程序操作第一偶数位线时，第二页缓冲器根据程序操作第二奇数位线，并且当第一页缓冲器操作第二页缓冲器时，第二页缓冲器根据程序操作第二偶数位线 根据程序的第一个奇数位线。

    Nonvolatile memory device
    7.
    发明授权
    Nonvolatile memory device 有权
    非易失性存储器件

    公开(公告)号：US08743602B2

    公开(公告)日：2014-06-03

    申请号：US13337200

    申请日：2011-12-26

    Applicant: Hyung-Min Lee

    Inventor： Hyung-Min Lee

    IPC: G11C11/34

    CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

    Abstract: Embodiments of present invention relate to a nonvolatile memory device that includes a first page buffer controlling any one of a first even bit line and a first odd bit line; a second page buffer controlling any one of a second even bit line and a second odd bit line; wherein the second page buffer operates the second odd bit line according to program when the first page buffer operates the first even bit line according to program, and the second page buffer operates the second even bit line according to program when the first page buffer operates the first odd bit line according to program.

    Abstract translation: 本发明的实施例涉及一种非易失性存储器件，其包括控制第一偶数位线和第一奇数位线中的任何一个的第一页缓冲器; 第二页缓冲器，其控制第二偶数位线和第二奇数位线中的任何一个; 其中当第一页缓冲器根据程序操作第一偶数位线时，第二页缓冲器根据程序操作第二奇数位线，并且当第一页缓冲器操作第二页缓冲器时，第二页缓冲器根据程序操作第二偶数位线 根据程序的第一个奇数位线。

    SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
    半导体存储器件及其工作方法

    公开(公告)号：US20120327718A1

    公开(公告)日：2012-12-27

    申请号：US13531998

    申请日：2012-06-25

    Applicant: Hyung Min LEE

    Inventor： Hyung Min LEE

    IPC: G11C16/10

    CPC classification number: G11C16/06 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/345

    Abstract: An operating method of a semiconductor memory device includes performing a first LSB program loop for storing first LSB data in first memory cells of a word line, performing a second LSB program loop for storing second LSB data in second memory cells of the selected word line and for detecting over-erased memory cells having threshold voltages lower than an over-erase reference voltage of a negative potential to raise the threshold voltages to be higher than the over-erase reference voltage, performing a first MSB program loop for storing first MSB data in the first memory cells, and performing a second MSB program loop for storing second MSB data in the second memory cells.

    Abstract translation: 半导体存储器件的操作方法包括：执行第一LSB程序循环，用于将第一LSB数据存储在字线的第一存储单元中，执行用于将第二LSB数据存储在所选字线的第二存储器单元中的第二LSB程序循环;以及 用于检测具有低于负电位的过擦除参考电压的阈值电压的过擦除存储器单元，以将阈值电压升高到高于过擦除参考电压，执行用于存储第一MSB数据的第一MSB程序循环 第一存储器单元，并且执行用于在第二存储器单元中存储第二MSB数据的第二MSB程序循环。

    Driving apparatus for display
    9.
    发明授权
    Driving apparatus for display 有权
    显示驱动装置

    公开(公告)号：US07764212B2

    公开(公告)日：2010-07-27

    申请号：US11930850

    申请日：2007-10-31

    Applicant: Hyung-Min Lee ,  Gyu Hyeong Cho ,  Young-Suk Son ,  Yong-Joon Jeon ,  Jin Yong Jeon ,  Seung-Chul Jung

    Inventor： Hyung-Min Lee ,  Gyu Hyeong Cho ,  Young-Suk Son ,  Yong-Joon Jeon ,  Jin Yong Jeon ,  Seung-Chul Jung

    IPC: H03M1/66

    CPC classification number: H03M1/682 ,  G09G3/20 ,  G09G2310/027 ,  G09G2320/0276 ,  G09G2330/028 ,  H03M1/765

    Abstract: A driving apparatus for a display is provided. The driving apparatus for a display comprises a reference voltage generator, a digital-to-analog converter, and an output unit. The reference voltage generator generates a plurality of reference voltages, and receives a difference value between two adjacent reference voltages and generates a plurality of sub reference voltages. The digital-to-analog converter selects one of the reference voltages and outputs the selected reference voltage as a first analog signal. The digital-to-analog converter selects one of the sub reference voltages and outputs the selected reference voltage as a second analog signal. The output unit processes, by addition or subtraction, the first and second analog signals for output.

    Abstract translation: 提供了一种用于显示器的驱动装置。 用于显示器的驱动装置包括参考电压发生器，数模转换器和输出单元。 参考电压发生器产生多个参考电压，并且接收两个相邻参考电压之间的差值，并产生多个子参考电压。 数模转换器选择参考电压之一并输出所选择的参考电压作为第一模拟信号。 数模转换器选择一个子参考电压，并输出所选择的参考电压作为第二模拟信号。 输出单元通过加法或减法处理第一和第二模拟信号以进行输出。

    DRIVING APPARATUS FOR DISPLAY
    10.
    发明申请
    DRIVING APPARATUS FOR DISPLAY 审中-公开
    驱动装置用于显示

    公开(公告)号：US20090051676A1

    公开(公告)日：2009-02-26

    申请号：US11930888

    申请日：2007-10-31

    Applicant: Gyu Hyeong Cho ,  Hyung-Min Lee ,  Young-Suk Son ,  Yong-Joon Jeon ,  Jin Yong Jeon ,  Seung-Chui Jung

    Inventor： Gyu Hyeong Cho ,  Hyung-Min Lee ,  Young-Suk Son ,  Yong-Joon Jeon ,  Jin Yong Jeon ,  Seung-Chui Jung

    IPC: G09G5/00 ,  H03M1/66

    CPC classification number: H03M1/002 ,  G09G3/20 ,  G09G2310/027 ,  G09G2320/0276 ,  G09G2330/028 ,  H03M1/765

    Abstract: A driving apparatus for a display is provided. The driving apparatus for a display comprises: a digital/analog converter for receiving an input voltage lower than a source voltage used in a buffer amplifier for output driving, generating a plurality of reference voltages, and selecting a reference voltage corresponding to an M (M is a positive integer) bit data signal; and an amplifier for amplifying the reference voltage selected by the digital/analog converter. Therefore, a circuit area and power consumption of the driving apparatus for a display can be minimized.

    Abstract translation: 提供了一种用于显示器的驱动装置。 用于显示器的驱动装置包括：数字/模拟转换器，用于接收低于用于输出驱动的缓冲放大器中使用的源电压的输入电压，产生多个参考电压，以及选择对应于M（M 是一个正整数）位数据信号; 以及用于放大由数字/模拟转换器选择的参考电压的放大器。 因此，可以使用于显示器的驱动装置的电路面积和功耗最小化。

Patent Agency Ranking