公开(公告)号：US20090022317A1

公开(公告)日：2009-01-22

申请号：US12169086

申请日：2008-07-08

申请人： Isao AKIMA ,  Tatsuya HARA ,  Eiji NATORI ,  Kazuo TANAKA ,  Masahiro TAKEUCHI

发明人： Isao AKIMA ,  Tatsuya HARA ,  Eiji NATORI ,  Kazuo TANAKA ,  Masahiro TAKEUCHI

IPC分类号： H04L9/06

CPC分类号： B60R25/04 ,  B60R25/24 ,  G07C9/00182 ,  G07C2009/0023 ,  G07C2009/00793 ,  H04L9/3226 ,  H04L2209/84

摘要： A vehicle security system includes a reception device that is mounted on a vehicle, and a transmission device that remotely operates the vehicle. The transmission device includes an encryption section that encrypts identification information that identifies the transmission device with a first encryption key, and a transmission section that transmits to the reception device instruction information that includes the identification information encrypted and gives an operation instruction to the reception device. The reception device includes a FeRAM that stores a second encryption key to pair with the first encryption key, wherein the second encryption key is erased from the FeRAM when the second encryption key is read out from the FeRAM, a reception section that receives the instruction information transmitted from the transmission device, a decoding section that decodes the identification information received, which is encrypted with the first encryption key and included in the received instruction information, with the second encryption key that is supposed to be stored in the FeRAM, and a judgment section that judges based on the decoded identification information as to whether the transmission device matches with the reception device.

摘要翻译： 车辆安全系统包括安装在车辆上的接收装置和远程操作车辆的发送装置。 发送装置包括：加密部，其利用第一加密密钥对识别发送装置的识别信息进行加密;发送部，向接收装置发送包含加密的识别信息的指示信息，并向接收装置发送操作指示。 接收装置包括存储与第一加密密钥配对的第二加密密钥的FeRAM，其中当从FeRAM读出第二加密密钥时，从FeRAM擦除第二加密密钥;接收指令信息的接收部分 从发送装置发送的解码部分，将接收到的识别信息用第一加密密钥加密并包含在接收到的指令信息中的解码部分与假定存储在FeRAM中的第二加密密钥进行解码， 基于解码的识别信息判断发送装置是否与接收装置相匹配的部分。

公开(公告)号：US20080229316A1

公开(公告)日：2008-09-18

申请号：US12045206

申请日：2008-03-10

申请人： Isao Akima

发明人： Isao Akima

IPC分类号： G06F9/46

CPC分类号： G06T5/20

摘要： A data processing device includes: an execution unit; and a memory unit, wherein the memory unit stores a plurality of pre-processing data on which a processing is to be rendered at a plurality of times prior to a specified time; (1) when a value of specified pre-processing data at the specified time is in a range between a maximum value and a minimum value among values of the plurality of pre-processing data, the execution unit renders the processing on the specified pre-processing data; and (2) when the value of the specified pre-processing data is greater than the maximum value or smaller than the minimum value, the execution unit renders the processing on an arbitrary value that is deemed substantively in the range between the maximum value and the minimum value, instead of the value of the specified pre-processing data.

摘要翻译： 一种数据处理装置，包括：执行单元; 以及存储单元，其中所述存储单元在指定时间之前多次存储要在其上呈现处理的多个预处理数据; （1）在所述规定时间的指定预处理数据的值处于所述多个预处理数据的值之间的最大值与最小值之间的范围内时，所述执行单元对所述预处理数据进行处理， 处理数据; 和（2）当指定的预处理数据的值大于最大值或小于最小值时，执行单元对在最大值和最小值之间的范围内实质上认为的任意值进行处理 最小值，而不是指定的预处理数据的值。

公开(公告)号：US20060119553A1

公开(公告)日：2006-06-08

申请号：US11285830

申请日：2005-11-22

申请人： Isao Akima

发明人： Isao Akima

IPC分类号： G09G3/30

CPC分类号： G09G3/32 ,  G09G3/2014 ,  G09G2310/0272 ,  G09G2320/066 ,  G09G2330/02

摘要： A display module enabling recognition of an image when the entire screen is bright (or dark). A current drive circuit includes a current amount control circuit for controlling the amount of current supplied from a high potential power supply to a transmission path in response to a current control signal. A drive current generation circuit controls the amount of current flowing through a transmission line in accordance with a gray scale value of video data based on RGB pulse width modulation signals. Current, which corresponds to the difference between the current of the current amount control circuit and the current controlled by the drive current generation circuit, flows through the transmission line. When using the drive current of the drive current generation circuit as a base current, the current amount control circuit adds current to the drive current with the current control signal.

摘要翻译： 当整个屏幕亮（或暗）时，能够识别图像的显示模块。 电流驱动电路包括电流量控制电路，用于响应于电流控制信号控制从高电位电源提供给传输路径的电流量。 驱动电流产生电路根据RGB脉宽调制信号，根据视频数据的灰度值控制流经传输线的电流量。 对应于电流量控制电路的电流与由驱动电流产生电路控制的电流之间的差值的电流流过传输线。 当使用驱动电流产生电路的驱动电流作为基极电流时，电流量控制电路利用电流控制信号将电流加到驱动电流上。

公开(公告)号：US20080292098A1

公开(公告)日：2008-11-27

申请号：US12124313

申请日：2008-05-21

申请人： Isao AKIMA ,  Tatsuya HARA ,  Eiji NATORI ,  Kazuo TANAKA

发明人： Isao AKIMA ,  Tatsuya HARA ,  Eiji NATORI ,  Kazuo TANAKA

IPC分类号： H04L9/28

CPC分类号： H04L9/0894 ,  H04L2209/84

摘要： A communication system includes: a transmission device; and a reception device, wherein the transmission device includes an encryption section that encrypts a plaintext to be transmitted to the reception device with a first encryption key, and a transmission section that transmits the encrypted plaintext to the reception device; and the reception device includes a FeRAM that stores a second encryption key to pair with the first encryption key, wherein, upon reading out the second encryption key from the FeRAM, the second encryption key is erased from the FeRAM, a reception section that receives the encrypted plaintext from the transmission device, and a decoding section that decodes the received plaintext encrypted with the first encryption key with the second encryption key that is supposed to be stored in the FeRAM.

摘要翻译： 通信系统包括：发送装置; 以及接收装置，其中，所述发送装置包括：加密部，其利用第一加密密钥对要发送到所述接收装置的明文进行加密;以及发送部，其将所述加密的明文发送到所述接收装置; 并且接收装置包括存储与第一加密密钥配对的第二加密密钥的FeRAM，其中，从FeRAM读出第二加密密钥时，从FeRAM擦除第二加密密钥，接收部分 来自发送装置的加密明文;以及解码部，其利用假定存储在FeRAM中的第二加密密钥对接收到的用第一加密密钥加密的明文进行解码。

公开(公告)号：US20080186787A1

公开(公告)日：2008-08-07

申请号：US12023138

申请日：2008-01-31

申请人： Isao AKIMA ,  Jinichi NAKAMURA

发明人： Isao AKIMA ,  Jinichi NAKAMURA

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C11/22 ,  G11C2029/0411

摘要： A storage device includes: a ferroelectric memory that temporarily stores data, wherein the ferroelectric memory stores an error correction code that is used for verifying the data by correcting errors possibly occurring on the data stored; a storage medium that has a plurality of storage regions and continually stores the data in one of the plurality of storage regions; and a control section that (1) writes the data and the error correction code to the ferroelectric memory, (2) writes the data written in the ferroelectric memory to one of the storage regions in the storage medium, (3) compares the data that is written in the ferroelectric memory and has been verified by using the error correction code written in the ferroelectric memory with the data written to the one of the storage regions in the storage medium, and (4) rewrites the data that has been verified to another one of the storage regions in the storage medium when both of the data do not match each other.

摘要翻译： 存储装置包括：临时存储数据的铁电存储器，其中所述铁电存储器存储用于通过校正可能发生在所存储的数据上的错误来验证数据的纠错码; 存储介质，其具有多个存储区域，并且将数据连续地存储在所述多个存储区域中的一个中; （1）将数据和纠错码写入铁电存储器，（2）将写入铁电存储器的数据写入存储介质中的一个存储区域，（3）将数据与 写入铁电存储器中，并且通过使用写入铁电体存储器中的纠错码将写入存储介质中的一个存储区域的数据进行验证，以及（4）将已验证的数据重写为另一个 当两个数据彼此不匹配时，存储介质中的一个存储区域。

公开(公告)号：US5266834A

公开(公告)日：1993-11-30

申请号：US915761

申请日：1992-07-21

申请人： Kunihiko Nishi ,  Michio Tanimoto ,  Toshihiro Yasuhara ,  Katsuhiro Tabata ,  Yasuhiro Yoshikawa ,  Isao Akima ,  Souichi Kunito ,  Toshio Nosaka ,  Hideaki Nakamura

发明人： Kunihiko Nishi ,  Michio Tanimoto ,  Toshihiro Yasuhara ,  Katsuhiro Tabata ,  Yasuhiro Yoshikawa ,  Isao Akima ,  Souichi Kunito ,  Toshio Nosaka ,  Hideaki Nakamura

IPC分类号： H01L23/495 ,  H01L25/10 ,  H01L23/02

CPC分类号： H01L23/4951 ,  H01L23/49568 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73215 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/3511

摘要： A package is provided for achieving higher packing density and higher circuit integration of memories, in particular, a structure is provided having a plurality of thin, surface mount packages which are stacked up. Each of the laminated packages includes a semiconductor pellet, leads fixed to the front surface of the pellet, a radiating plate fixed to the rear surface of the same, and a resin mold member. To achieve a stabilized laminated structure, the mold member is shaped into a convex form on the front side of the pellet and into a concave form on the rear side of the same, so that the concave portion of one package can engage with the convex portion of another package.

摘要翻译： 提供了用于实现更高的堆积密度和更高的存储器电路集成的封装，特别地，提供了具有堆叠的多个薄的表面贴装封装的结构。 每个层叠包装包括半导体颗粒，固定在颗粒的前表面的引线，固定到其后表面的散热板和树脂模制构件。 为了实现稳定的层压结构，模具构件在颗粒的前侧成形为凸形，并且在其后侧成为凹形，使得一个包装的凹部能够与凸部接合 的另一个包。

公开(公告)号：US20080189507A1

公开(公告)日：2008-08-07

申请号：US12024340

申请日：2008-02-01

申请人： Isao AKIMA

发明人： Isao AKIMA

IPC分类号： G06F12/02

CPC分类号： G06F9/3017 ,  G06F1/03

摘要： A program execution device includes: a lookup table storage section that stores a lookup table stipulating a plurality of relations between a plurality of input data and a plurality of output data that are results of operation conducted on the plurality of input data; a program storage section that stores a program including a command directing to obtain one of the output data that is a result of the operation conducted on one of the input data, which is defined by the one of the input data and the operation; and a program execution section having a first cycle of designating the one of the input data in the command to the lookup table in the lookup table storage section, and a second cycle of receiving the one of the output data corresponding to the one of the input data from the lookup table.

摘要翻译： 程序执行装置包括：查找表存储部，其存储规定多个输入数据与作为对多个输入数据进行的操作结果的多个输出数据之间的多个关系的查找表; 程序存储部分，存储包括命令的命令的指令，以获得作为对由输入数据和操作之一定义的输入数据之一进行的操作的结果的输出数据之一; 以及程序执行部，具有将命令中的输入数据中的一个指定给查找表存储部中的查找表的第一周期，以及接收与输入的对应的输出数据中的一个的第二周期 查询表中的数据。

公开(公告)号：US07164404B2

公开(公告)日：2007-01-16

申请号：US10625843

申请日：2003-07-24

申请人： Michiru Senda ,  Isao Akima

发明人： Michiru Senda ,  Isao Akima

IPC分类号： G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/32 ,  G09G3/3659 ,  G09G3/3688 ,  G09G2300/0828 ,  G09G2300/0876 ,  G09G2310/027 ,  G09G2340/145

摘要： A digital image signal is serially transferred to each of pixels through a drain signal line. The digital image signal is sampled at pixel selecting transistors, converted from a serial signal to a parallel signal, and then converted to an analog image signal by a DA converter. This DA converter includes a plurality of capacitor electrodes coupled to a pixel electrode at a weighted capacitance ratio and a clock supplying portion for supplying periodic clock signals to the plurality of the capacitor electrodes in response to the digital image signal. The analog image signal is applied to the pixel electrode. This simplifies a configuration of peripheral circuits of the pixel, and accordingly reduces the frame area of a panel and the number of wiring lines.

摘要翻译： 数字图像信号通过漏极信号线串行传输到每个像素。 数字图像信号在像素选择晶体管被采样，从串行信号转换成并行信号，然后由DA转换器转换为模拟图像信号。 该DA转换器包括以加权电容比耦合到像素电极的多个电容器电极和用于响应于数字图像信号向多个电容器电极提供周期性时钟信号的时钟提供部分。 模拟图像信号被施加到像素电极。 这简化了像素的外围电路的配置，并且因此减小了面板的框架面积和布线数量。

公开(公告)号：US20050231535A1

公开(公告)日：2005-10-20

申请号：US11105581

申请日：2005-04-14

申请人： Isao Akima

发明人： Isao Akima

IPC分类号： H01L51/50 ,  G09G3/20 ,  G09G3/22 ,  G09G3/30 ,  G09G3/32 ,  H04N5/66 ,  H04N5/70 ,  H05B33/14 ,  G09G5/00

CPC分类号： G09G3/3283 ,  G09G3/2014 ,  G09G3/22 ,  G09G3/32 ,  G09G3/3241 ,  G09G2320/0233

摘要： The variation of the electric current fed to the luminescent element is prevented in the display device with the electric current driven luminescent element, achieving uniform display brightness. The pulse width modulation circuit 10 generating a pulse width modulation signal SRP, the pulse of which is modulated for a certain period according to the image data, and the electric current generation circuit 20 generating the pulse current I corresponding the pulse width modulation signal are formed. The pulse current I is supplied to the electric current driven luminescent elements L1 and L2 through the pixel selection TFT 51, 52. Since the pulse current I is stable and at a certain level, it is not influenced by the variation among the pixels due to the manufacturing process, achieving uniform display brightness and improved display quality.

摘要翻译： 在具有电流驱动的发光元件的显示装置中，防止馈送到发光元件的电流的变化，实现均匀的显示亮度。 形成脉冲宽度调制电路10，其产生脉冲宽度调制信号SRP，脉冲宽度调制信号SRP根据图像数据调制一定时间，电流产生电路20产生对应于脉宽调制信号的脉冲电流I 。 脉冲电流I通过像素选择TFT51,52被提供给电流驱动发光元件L 1和L 2。 由于脉冲电流I稳定并处于一定水平，所以不受制造工艺中的像素之间的变化的影响，实现均匀的显示亮度和显示质量的提高。

公开(公告)号：US4509147A

公开(公告)日：1985-04-02

申请号：US383945

申请日：1982-06-01

申请人： Nobuyoshi Tanimura ,  Sho Yamamoto ,  Kazuo Yoshizaki ,  Isao Akima

发明人： Nobuyoshi Tanimura ,  Sho Yamamoto ,  Kazuo Yoshizaki ,  Isao Akima

IPC分类号： G11C7/06 ,  G11C11/419 ,  H03F3/45 ,  H03F3/72 ,  G11C11/34

CPC分类号： H03F3/72 ,  G11C11/419 ,  G11C7/06 ,  H03F3/45475

摘要： In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained. The operating speed of the RAM can be raised owing to the fact that the dissymmetric type differential amplifier circuit having an active load circuit exhibits a comparatively high gain and the fact that the signal amplification by the balanced circuit is permitted.

摘要翻译： 在静态RAM中，读出放大器包括第一和第二非对称型差分放大器电路，每个差分放大器具有一对差分晶体管和有源负载电路，例如连接到差分晶体管的漏极的电流镜电路。 从存储单元发送的平衡信号中的一个被提供给第一非对称型差分放大器电路的非反相输入端子和第二非对称型差分放大器电路的反相输入端子。 所述平衡信号中的另一个被施加到第一和第二非对称型差分放大器电路的剩余输入端。 结果，尽管不能从每个非对称型差分放大器电路输出平衡信号，但是可以获得放大的平衡信号。 由于具有有源负载电路的非对称型差分放大器电路具有相对较高的增益以及允许由平衡电路进行信号放大的事实，所以可以提高RAM的工作速度。