摘要:
A processor, system, and method are disclosed. In an embodiment, the processor includes a first site and a second site. There is a link to transmit a voltage stabilization signal from the second site to the first site. In the first site voltage correction logic can dynamically modify a voltage supplied to the first site and second site. In the second site there is logic to assert the voltage stabilization signal. After asserting the voltage stabilization signal, the second site is granted at least a window of time in which the supplied voltage to the second site does not change.
摘要:
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.
摘要:
Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
摘要:
Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
摘要:
A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache.
摘要:
Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
摘要:
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.
摘要:
A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache.
摘要:
A method, system, and apparatus to enable at least one active core in a multi-core processor to operate at a higher operating point while at least one other core in the multi-core processor is in an idle state. When the idle core exits the idle state, the operating point may be reduced after a hysteresis timer has expired.
摘要:
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.