公开(公告)号：US20130086536A1

公开(公告)日：2013-04-04

申请号：US13616507

申请日：2012-09-14

申请人： WOOK KIM ,  HYUNG OCK KIM ,  JUNG YUN CHOI ,  KEE SUP KIM ,  HYO SIG WON

发明人： WOOK KIM ,  HYUNG OCK KIM ,  JUNG YUN CHOI ,  KEE SUP KIM ,  HYO SIG WON

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of constructing a standard cell library for double patterning lithography (DPL) includes dividing a standard cell into a first region determined not to have an interaction with an adjacent outer cell and a second region that is likely to have such an interaction, generating data representative of DPL patterns corresponding to the first and second regions, and generating a standard cell library made up of the data. The library is then accessed and used to form a DPL mask. The DPL mask can be used to form a pattern on a substrate made up of a layout of cells in which the pattern of the standard cell is duplicated at several locations in the layout.

摘要翻译： 构建用于双重图案化光刻（DPL）的标准单元库的方法包括将标准单元划分成确定为不与相邻外单元相互作用的第一区域和可能具有这种相互作用的第二区域，生成数据 代表对应于第一和第二区域的DPL模式，以及生成由数据组成的标准单元库。 然后，库被访问并用于形成DPL掩码。 DPL掩模可用于在由其中在布局中的多个位置处复制标准单元的图案的单元布局构成的基板上形成图案。

公开(公告)号：US20070291606A1

公开(公告)日：2007-12-20

申请号：US11670634

申请日：2007-02-02

申请人： Jung Yun CHOI

发明人： Jung Yun CHOI

IPC分类号： G11B7/00

CPC分类号： G11B7/1267 ,  G11B7/0045

摘要： A power control process in which an inner region optimum power control (“OPC”) value of an inner region of an optical disc is measured at a base speed is selectively performed. A predicted outer region OPC value is calculated based upon the inner region OPC value, a reference laser power associated with the base speed and a desired maximum speed. The predicted outer region OPC value is compared with a laser power limit, and whether to measure an outer region OPC value on an outer region of the optical disc at a desired maximum speed is determined.

摘要翻译： 选择性地执行其中以基本速度测量光盘的内部区域的内部区域最佳功率控制（“OPC”）值的功率控制处理。 基于内部区域OPC值，与基准速度相关联的参考激光功率和期望的最大速度来计算预测的外部区域OPC值。 将预测的外部区域OPC值与激光功率限制进行比较，并且确定是否以期望的最大速度测量光盘的外部区域上的外部区域OPC值。

公开(公告)号：US08659316B2

公开(公告)日：2014-02-25

申请号：US13603878

申请日：2012-09-05

申请人： Hyung Ock Kim ,  Jae Han Jeon ,  Jung Yun Choi ,  Hyo Sig Won ,  Kyu Myung Choi

发明人： Hyung Ock Kim ,  Jae Han Jeon ,  Jung Yun Choi ,  Hyo Sig Won ,  Kyu Myung Choi

IPC分类号： H03K17/16 ,  H03K19/003 ,  H02J3/14 ,  H01H35/00

CPC分类号： H03K19/0016 ,  H03K19/00361 ,  Y10T307/461 ,  Y10T307/951

摘要： A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.

摘要翻译： 功率控制电路连接在电源电压和逻辑电路之间，以切换提供给逻辑电路的电力。 功率控制电路包括并联接收外部模式改变信号的多个第一功率门控单元（PGC），与一个第一PGC连接的至少一个第二PGC，与至少一个第二PGC连接的至少一个第三PGC，以及 与所述至少一个第三PGC连接的至少一个第四PGC。 第二电源门控单元，第三PGC和/或第四PGC可以包括多个门控单元。 第二，第三和第四多个中的至少一个具有串联连接的电力门控单元。 第一至第四PGC中的每一个响应于模式改变信号而切换供电。

公开(公告)号：US20130185692A1

公开(公告)日：2013-07-18

申请号：US13626121

申请日：2012-09-25

申请人： Hyung-Ock KIM ,  Jae-Han JEON ,  Jung-Yun CHOI ,  Kee-Sup KIM ,  Hyo-Sig WON

发明人： Hyung-Ock KIM ,  Jae-Han JEON ,  Jung-Yun CHOI ,  Kee-Sup KIM ,  Hyo-Sig WON

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045 ,  G06F2217/84 ,  H01L27/0207

摘要： In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.

摘要翻译： 在设计片上系统的方法中，包括应用了身体偏置的无电话标准单元，通过反转向前的方式，调整慢转角定时参数以增加片上系统的运行速度分布的缓慢的转角 主体偏置和快速转角定时参数被调整，以通过反射反向主体偏置来减小片上系统的运行速度分布的快速转角。 基于对应于增加的慢转角的调整的慢转角定时参数和对应于减小的快速拐角的经调整的快速角定时参数，实现包括无tapless标准单元的片上系统。 慢转角定时参数对应于片上系统的运行速度设计窗口的最低值，快速转角定时参数对应于片上系统的运行速度设计窗口的最高值。

公开(公告)号：US08013628B2

公开(公告)日：2011-09-06

申请号：US12381431

申请日：2009-03-12

申请人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

发明人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04B15/02 ,  H04B2215/064

摘要： A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

摘要翻译： 具有有源时钟屏蔽结构的电路包括接收时钟信号并基于时钟信号执行逻辑运算的逻辑电路，基于时钟信号切换逻辑电路的模式的功率门控电路，基于 电源门控信号，将时钟信号发送到逻辑电路的时钟信号传输线，以及至少一个电源门控信号传输线，其将电源门控信号发送到电源门控电路并用作与时钟的屏蔽线对 信号传输线。

公开(公告)号：US20090008740A1

公开(公告)日：2009-01-08

申请号：US12165827

申请日：2008-07-01

申请人： Bong-Hyun Lee ,  Jung-Yun Choi

发明人： Bong-Hyun Lee ,  Jung-Yun Choi

IPC分类号： H01L27/105

CPC分类号： H01L21/74 ,  H01L21/28123 ,  H01L21/823892 ,  H01L27/0928

摘要： A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern.

摘要翻译： 半导体集成电路器件包括半导体衬底; 在半导体衬底上沿一个方向延伸的虚拟图案; 将虚设图案电连接到半导体衬底的接合区域; 以及电压施加单元，被配置为向所述虚拟图案施加偏置电压。

公开(公告)号：US08621399B2

公开(公告)日：2013-12-31

申请号：US13458516

申请日：2012-04-27

申请人： Kyung-Tae Do ,  Yong-Seok Lee ,  Hyo-Sig Won ,  Jung-Yun Choi ,  Jong-Ho Kim

发明人： Kyung-Tae Do ,  Yong-Seok Lee ,  Hyo-Sig Won ,  Jung-Yun Choi ,  Jong-Ho Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.

摘要翻译： 在设计半导体器件的方法中，可以选择包括在半导体器件的布局中的晶体管。 可以设置偏置数据以改变所选择的晶体管的特性。 可以在忽略偏置数据之后执行用于半导体器件的布局的设计规则检查（DRC）处理。 可以基于偏置数据执行用于半导体器件的布局的光学邻近校正（OPC）处理。

公开(公告)号：US20130069690A1

公开(公告)日：2013-03-21

申请号：US13603878

申请日：2012-09-05

申请人： Hyung Ock KIM ,  Jae Han JEON ,  Jung Yun CHOI ,  Hyo Sig WON ,  Kyu Myung CHOI

发明人： Hyung Ock KIM ,  Jae Han JEON ,  Jung Yun CHOI ,  Hyo Sig WON ,  Kyu Myung CHOI

IPC分类号： H03K17/16

CPC分类号： H03K19/0016 ,  H03K19/00361 ,  Y10T307/461 ,  Y10T307/951

摘要： A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.

摘要翻译： 功率控制电路连接在电源电压和逻辑电路之间，以切换提供给逻辑电路的电力。 功率控制电路包括并联接收外部模式改变信号的多个第一功率门控单元（PGC），与一个第一PGC连接的至少一个第二PGC，与至少一个第二PGC连接的至少一个第三PGC，以及 与所述至少一个第三PGC连接的至少一个第四PGC。 第二电源门控单元，第三PGC和/或第四PGC可以包括多个门控单元。 第二，第三和第四多个中的至少一个具有串联连接的电力门控单元。 第一至第四PGC中的每一个响应于模式改变信号而切换供电。

公开(公告)号：US20120313693A1

公开(公告)日：2012-12-13

申请号：US13491110

申请日：2012-06-07

申请人： Kyung Tae Do ,  Hyung Ock Kim ,  Hyo Sig Won ,  Jung Yun Choi

发明人： Kyung Tae Do ,  Hyung Ock Kim ,  Hyo Sig Won ,  Jung Yun Choi

IPC分类号： G05F3/02

CPC分类号： G06F1/26 ,  G06F1/04 ,  G06F1/32

摘要： A method of controlling the provision of a body bias voltage to a logic gate region of a semiconductor device includes; gating application of a clock signal applied to a synchronization element in the logic gate region in accordance with an enable signal, and providing the body bias voltage to each body terminal of a plurality of logic gates arranged in the logic gate region in accordance with the enable signal.

摘要翻译： 控制向半导体器件的逻辑栅极区域提供体偏置电压的方法包括： 根据使能信号门控施加到逻辑门区域中的同步元件的时钟信号，并根据该使能信号向布置在逻辑门区域中的多个逻辑门极的每个主体端子提供体偏置电压 信号。

公开(公告)号：US08156460B2

公开(公告)日：2012-04-10

申请号：US12547729

申请日：2009-08-26

申请人： Kyung-Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

发明人： Kyung-Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： In a method of estimating a leakage current in a semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of a cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function of a segment is generated by arithmetically operating the virtual cell leakage characteristic functions of all cells in the segment. Then, a full chip leakage characteristic function of the chip is generated by statistically operating the segment leakage characteristic functions of all segments in the chip. Accordingly, computational loads of Wilkinson's method for generating the full chip leakage characteristic function can remarkably be reduced.

摘要翻译： 在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。 空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。 通过算术运算实际泄漏特性函数产生单元的虚拟单元泄漏特性函数。 通过对片段中所有单元的虚拟单元泄漏特性函数进行算术运算，产生段的段泄漏特性函数。 然后，通过统计操作芯片中所有段的段泄漏特性函数来产生芯片的全芯片泄漏特性功能。 因此，Wilkinson用于产生全芯片泄漏特性功能的方法的计算负载可以显着降低。