公开(公告)号：US20160322097A1

公开(公告)日：2016-11-03

申请号：US15009149

申请日：2016-01-28

申请人： In-Sub SHIN ,  Jae-Han JEON ,  Hyung-Ock KIM

发明人： In-Sub SHIN ,  Jae-Han JEON ,  Hyung-Ock KIM

IPC分类号： G11C11/417

CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C5/148 ,  G11C7/1006

摘要： A system-on-chip and an electronic device including the system-on-chip are provided. The system-on-chip includes a power switch, a logic block, a memory device, and a buffer. The power switch is coupled between a first power supply line and a virtual power supply line, and turns on in response to a switch control signal. The logic block is coupled between the virtual power supply line and a ground line. The memory device is coupled between a second power supply line and the ground line. The buffer is coupled between the second power supply line and the ground line, and generates the switch control signal based on a sleep signal.

摘要翻译： 提供了片上系统和包括片上系统的电子设备。 片上系统包括电源开关，逻辑块，存储器件和缓冲器。 电源开关耦合在第一电源线和虚拟电源线之间，并且响应于开关控制信号而导通。 逻辑块耦合在虚拟电源线和地线之间。 存储器件耦合在第二电源线和接地线之间。 缓冲器耦合在第二电源线和接地线之间，并且基于睡眠信号产生开关控制信号。

公开(公告)号：US08659316B2

公开(公告)日：2014-02-25

申请号：US13603878

申请日：2012-09-05

申请人： Hyung Ock Kim ,  Jae Han Jeon ,  Jung Yun Choi ,  Hyo Sig Won ,  Kyu Myung Choi

发明人： Hyung Ock Kim ,  Jae Han Jeon ,  Jung Yun Choi ,  Hyo Sig Won ,  Kyu Myung Choi

IPC分类号： H03K17/16 ,  H03K19/003 ,  H02J3/14 ,  H01H35/00

CPC分类号： H03K19/0016 ,  H03K19/00361 ,  Y10T307/461 ,  Y10T307/951

摘要： A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.

摘要翻译： 功率控制电路连接在电源电压和逻辑电路之间，以切换提供给逻辑电路的电力。 功率控制电路包括并联接收外部模式改变信号的多个第一功率门控单元（PGC），与一个第一PGC连接的至少一个第二PGC，与至少一个第二PGC连接的至少一个第三PGC，以及 与所述至少一个第三PGC连接的至少一个第四PGC。 第二电源门控单元，第三PGC和/或第四PGC可以包括多个门控单元。 第二，第三和第四多个中的至少一个具有串联连接的电力门控单元。 第一至第四PGC中的每一个响应于模式改变信号而切换供电。

公开(公告)号：US20130185692A1

公开(公告)日：2013-07-18

申请号：US13626121

申请日：2012-09-25

申请人： Hyung-Ock KIM ,  Jae-Han JEON ,  Jung-Yun CHOI ,  Kee-Sup KIM ,  Hyo-Sig WON

发明人： Hyung-Ock KIM ,  Jae-Han JEON ,  Jung-Yun CHOI ,  Kee-Sup KIM ,  Hyo-Sig WON

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045 ,  G06F2217/84 ,  H01L27/0207

摘要： In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.

摘要翻译： 在设计片上系统的方法中，包括应用了身体偏置的无电话标准单元，通过反转向前的方式，调整慢转角定时参数以增加片上系统的运行速度分布的缓慢的转角 主体偏置和快速转角定时参数被调整，以通过反射反向主体偏置来减小片上系统的运行速度分布的快速转角。 基于对应于增加的慢转角的调整的慢转角定时参数和对应于减小的快速拐角的经调整的快速角定时参数，实现包括无tapless标准单元的片上系统。 慢转角定时参数对应于片上系统的运行速度设计窗口的最低值，快速转角定时参数对应于片上系统的运行速度设计窗口的最高值。

公开(公告)号：US20130086536A1

公开(公告)日：2013-04-04

申请号：US13616507

申请日：2012-09-14

申请人： WOOK KIM ,  HYUNG OCK KIM ,  JUNG YUN CHOI ,  KEE SUP KIM ,  HYO SIG WON

发明人： WOOK KIM ,  HYUNG OCK KIM ,  JUNG YUN CHOI ,  KEE SUP KIM ,  HYO SIG WON

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of constructing a standard cell library for double patterning lithography (DPL) includes dividing a standard cell into a first region determined not to have an interaction with an adjacent outer cell and a second region that is likely to have such an interaction, generating data representative of DPL patterns corresponding to the first and second regions, and generating a standard cell library made up of the data. The library is then accessed and used to form a DPL mask. The DPL mask can be used to form a pattern on a substrate made up of a layout of cells in which the pattern of the standard cell is duplicated at several locations in the layout.

摘要翻译： 构建用于双重图案化光刻（DPL）的标准单元库的方法包括将标准单元划分成确定为不与相邻外单元相互作用的第一区域和可能具有这种相互作用的第二区域，生成数据 代表对应于第一和第二区域的DPL模式，以及生成由数据组成的标准单元库。 然后，库被访问并用于形成DPL掩码。 DPL掩模可用于在由其中在布局中的多个位置处复制标准单元的图案的单元布局构成的基板上形成图案。

公开(公告)号：US20130069690A1

公开(公告)日：2013-03-21

申请号：US13603878

申请日：2012-09-05

申请人： Hyung Ock KIM ,  Jae Han JEON ,  Jung Yun CHOI ,  Hyo Sig WON ,  Kyu Myung CHOI

发明人： Hyung Ock KIM ,  Jae Han JEON ,  Jung Yun CHOI ,  Hyo Sig WON ,  Kyu Myung CHOI

IPC分类号： H03K17/16

CPC分类号： H03K19/0016 ,  H03K19/00361 ,  Y10T307/461 ,  Y10T307/951

摘要： A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.

摘要翻译： 功率控制电路连接在电源电压和逻辑电路之间，以切换提供给逻辑电路的电力。 功率控制电路包括并联接收外部模式改变信号的多个第一功率门控单元（PGC），与一个第一PGC连接的至少一个第二PGC，与至少一个第二PGC连接的至少一个第三PGC，以及 与所述至少一个第三PGC连接的至少一个第四PGC。 第二电源门控单元，第三PGC和/或第四PGC可以包括多个门控单元。 第二，第三和第四多个中的至少一个具有串联连接的电力门控单元。 第一至第四PGC中的每一个响应于模式改变信号而切换供电。

公开(公告)号：US20120313693A1

公开(公告)日：2012-12-13

申请号：US13491110

申请日：2012-06-07

申请人： Kyung Tae Do ,  Hyung Ock Kim ,  Hyo Sig Won ,  Jung Yun Choi

发明人： Kyung Tae Do ,  Hyung Ock Kim ,  Hyo Sig Won ,  Jung Yun Choi

IPC分类号： G05F3/02

CPC分类号： G06F1/26 ,  G06F1/04 ,  G06F1/32

摘要： A method of controlling the provision of a body bias voltage to a logic gate region of a semiconductor device includes; gating application of a clock signal applied to a synchronization element in the logic gate region in accordance with an enable signal, and providing the body bias voltage to each body terminal of a plurality of logic gates arranged in the logic gate region in accordance with the enable signal.

摘要翻译： 控制向半导体器件的逻辑栅极区域提供体偏置电压的方法包括： 根据使能信号门控施加到逻辑门区域中的同步元件的时钟信号，并根据该使能信号向布置在逻辑门区域中的多个逻辑门极的每个主体端子提供体偏置电压 信号。

公开(公告)号：US07948263B2

公开(公告)日：2011-05-24

申请号：US12719472

申请日：2010-03-08

申请人： Hyung-Ock Kim ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Mun-Jun Seo ,  Youngsoo Shin

发明人： Hyung-Ock Kim ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Mun-Jun Seo ,  Youngsoo Shin

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0016 ,  H03K19/0013

摘要： A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.

摘要翻译： 电源门控电路包括逻辑电路，开关元件和保持触发器。 逻辑电路耦合在第一电源轨和虚拟电源轨之间。 响应于指示活动模式或待机模式的模式控制信号，开关元件将虚拟电源轨选择性地耦合到第二电源轨。 保持触发器响应于虚拟电源轨的电压选择性地执行触发器操作或数据保持操作。

公开(公告)号：US20100231255A1

公开(公告)日：2010-09-16

申请号：US12719472

申请日：2010-03-08

申请人： Hyung-Ock Kim ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Jun Seomun ,  Youngsoo Shin

发明人： Hyung-Ock Kim ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Jun Seomun ,  Youngsoo Shin

IPC分类号： H03K19/003

CPC分类号： H03K19/0016 ,  H03K19/0013

摘要： A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.

摘要翻译： 电源门控电路包括逻辑电路，开关元件和保持触发器。 逻辑电路耦合在第一电源轨和虚拟电源轨之间。 响应于指示活动模式或待机模式的模式控制信号，开关元件将虚拟电源轨选择性地耦合到第二电源轨。 保持触发器响应于虚拟电源轨的电压选择性地执行触发器操作或数据保持操作。

公开(公告)号：US20080012424A1

公开(公告)日：2008-01-17

申请号：US11741995

申请日：2007-04-30

申请人： Youngsoo Shin ,  Hyung-Ock Kim

发明人： Youngsoo Shin ,  Hyung-Ock Kim

IPC分类号： H02J1/04

CPC分类号： G11C5/063 ,  Y10T307/383 ,  Y10T307/642

摘要： A low power semiconductor memory device using a power gating is disclosed. The semiconductor memory device includes a standard cell and a power gating cell. The standard cell is provided with a virtual supply voltage and a first supply voltage. The power gating cell generates the virtual supply voltage from a second supply voltage and provides the standard cell with the virtual supply voltage in response to a control signal. The virtual supply voltage and the first supply voltage are provided by a first metal layer and the second supply voltage is provided by a third metal layer. The power gating cell may include at least one slice block and isolator blocks. The respective slice block has a transistor for switching current. The isolator blocks are arranged on both sides of the slice block and insulate the slice block from outside.

摘要翻译： 公开了一种使用电源门控的低功率半导体存储器件。 半导体存储器件包括标准单元和电源门控单元。 标准单元具有虚拟电源电压和第一电源电压。 电源门控单元从第二电源电压产生虚拟电源电压，并响应于控制信号向标准单元提供虚拟电源电压。 虚拟电源电压和第一电源电压由第一金属层提供，第二电源电压由第三金属层提供。 功率门控单元可以包括至少一个切片块和隔离块。 各个切片块具有用于切换电流的晶体管。 隔离块被布置在切片块的两侧，并将切片块与外部绝缘。

公开(公告)号：US07755396B2

公开(公告)日：2010-07-13

申请号：US11741995

申请日：2007-04-30

申请人： Youngsoo Shin ,  Hyung-Ock Kim

发明人： Youngsoo Shin ,  Hyung-Ock Kim

IPC分类号： H01L25/00 ,  H03K19/00

CPC分类号： G11C5/063 ,  Y10T307/383 ,  Y10T307/642

摘要： A low power semiconductor memory device using a power gating is disclosed. The semiconductor memory device includes a standard cell and a power gating cell. The standard cell is provided with a virtual supply voltage and a first supply voltage. The power gating cell generates the virtual supply voltage from a second supply voltage and provides the standard cell with the virtual supply voltage in response to a control signal. The virtual supply voltage and the first supply voltage are provided by a first metal layer and the second supply voltage is provided by a third metal layer. The power gating cell may include at least one slice block and isolator blocks. The respective slice block has a transistor for switching current. The isolator blocks are arranged on both sides of the slice block and insulate the slice block from outside.

摘要翻译： 公开了一种使用电源门控的低功率半导体存储器件。 半导体存储器件包括标准单元和电源门控单元。 标准单元具有虚拟电源电压和第一电源电压。 电源门控单元从第二电源电压产生虚拟电源电压，并响应于控制信号向标准单元提供虚拟电源电压。 虚拟电源电压和第一电源电压由第一金属层提供，第二电源电压由第三金属层提供。 功率门控单元可以包括至少一个切片块和隔离块。 各个切片块具有用于切换电流的晶体管。 隔离块被布置在切片块的两侧，并将切片块与外部绝缘。