BROADLY TUNABLE SINGLE-MODE QUANTUM CASCADE LASER SOURCES AND SENSORS
    1.
    发明申请
    BROADLY TUNABLE SINGLE-MODE QUANTUM CASCADE LASER SOURCES AND SENSORS 有权
    广泛的单模单模量子CASCADE激光源和传感器

    公开(公告)号:US20080144677A1

    公开(公告)日:2008-06-19

    申请号:US11611819

    申请日:2006-12-15

    IPC分类号: H01S3/10

    摘要: A broadly tunable single-mode infrared laser source based on semiconductor lasers. The laser source has two parts: an array of closely-spaced DFB QCLs (or other semiconductor lasers) and a controller that can switch each of the individual lasers in the array on and off, set current for each of the lasers and, and control the temperature of the lasers in the array. The device can be used in portable broadband sensors to simultaneously detect a large number of compounds including chemical and biological agents. A microelectronic controller is combined with an array of individually-addressed DFB QCLs with slightly different DFB grating periods fabricated on the same broadband (or multiple wavelengths) QCL material. This allows building a compact source providing narrow-line broadly-tunable coherent radiation in the Infrared or Terahertz spectral range (as well as in the Ultraviolet and Visible spectral ranges, using semiconductor lasers with different active region design). The performance (tuning range, line width, power level) is comparable to that of external grating tunable semiconductor lasers, but the proposed design is much smaller and much easier to manufacture.

    摘要翻译: 基于半导体激光器的广泛可调单模红外激光源。 激光源具有两部分:紧密间隔的DFB QCL(或其他半导体激光器)的阵列以及能够切换阵列中各个激光器的每个开关的控制器,为每个激光器设置电流和控制 阵列中的激光器的温度。 该装置可用于便携式宽带传感器中以同时检测大量包括化学和生物试剂在内的化合物。 微电子控制器与在相同宽带(或多波长)QCL材料上制造的具有稍微不同的DFB光栅周期的单独寻址的DFB QCL阵列组合。 这样可以在红外或太赫兹光谱范围(以及使用具有不同有源区域设计的半导体激光器的紫外和可见光谱范围)中构建一个紧凑的源,提供窄线宽可调谐相干辐射。 性能(调谐范围,线宽,功率水平)与外部光栅可调谐半导体激光器的性能相当,但所提出的设计要小得多,制造容易得多。

    Configurable memory design for masked programmable logic

    公开(公告)号:US07000165B1

    公开(公告)日:2006-02-14

    申请号:US10269113

    申请日:2002-10-09

    IPC分类号: G01R31/28

    摘要: A mask programmable integrated circuit includes a read only memory (ROM), a random access memory (RAM), and a controller. The controller couples to the ROM and RAM. The controller senses a reset condition and, in response, directs a clear of the RAM or a preload of contents of the ROM to the RAM. The preload can be performed after a successful self-test of the RAM is achieved. The RAM has a variable word length and depth size and can be configured to operate in one of many modes. The integrated circuit further includes a first and a second multiplexer (MUX). The first MUX is interposed between the RAM and the ROM, and selectively couples either the ROM data or the built-in self-test (BIST) data to the first MUX output. The second MUX is interposed between the first MUX and the RAM, and selectively couples either the output of the first MUX or a (synchronous or asynchronous) data input to the RAM. With the preload feature, the invention can emulate a ROM, a preloaded RAM, or look-up table logic functions as well as conventional RAM. Further, BIST allows for testing of the RAM without the needs for external support.

    Configurable memory design for masked programmable logic
    3.
    发明授权
    Configurable memory design for masked programmable logic 有权
    可配置的可编程逻辑存储器设计

    公开(公告)号:US06492833B1

    公开(公告)日:2002-12-10

    申请号:US09302053

    申请日:1999-04-28

    IPC分类号: H01L2500

    摘要: A mask programmable integrated circuit includes a read only memory (ROM), a random access memory (RAM), and a controller. The controller couples to the ROM and RAM. The controller senses a reset condition and, in response, directs a clear of the RAM or a preload of contents of the ROM to the RAM. The preload can be performed after a successful self-test of the RAM is achieved. The RAM has a variable word length and depth size and can be configured to operate in one of many modes. The integrated circuit further includes a first and a second multiplexer (MUX). The first MUX is interposed between the RAM and the ROM, and selectively couples either the ROM data or the built-in self-test (BIST) data to the first MUX output. The second MUX is interposed between the first MUX and the RAM, and selectively couples either the output of the first MUX or a (synchronous or asynchronous) data input to the RAM. With the preload feature, the invention can emulate a ROM, a preloaded RAM, or looktip table logic functions as well as conventional RAM. Further, BIST allows for testing of the RAM without the needs for external support.

    摘要翻译: 掩模可编程集成电路包括只读存储器(ROM),随机存取存储器(RAM)和控制器。 控制器耦合到ROM和RAM。 控制器检测到复位条件,并且作为响应,将RAM的清除或ROM的内容的预加载引导到RAM。 可以在实现RAM的成功自检之后执行预载。 RAM具有可变的字长和深度大小,可以配置为在许多模式之一下运行。 集成电路还包括第一和第二多路复用器(MUX)。 第一MUX被插入在RAM和ROM之间,并且将ROM数据或内置自检(BIST)数据选择性地耦合到第一MUX输出。 第二MUX插入在第一MUX和RAM之间,并且将第一MUX的输出或(同步或异步)数据输入选择性地耦合到RAM。 利用预加载功能,本发明可以模拟ROM,预加载的RAM或查询表逻辑功能以及常规的RAM。 此外,BIST允许对RAM进行测试,而无需外部支持。

    Direct coal liquefaction with integrated product hydrotreating and catalyst cascading
    5.
    发明申请
    Direct coal liquefaction with integrated product hydrotreating and catalyst cascading 有权
    直接煤液化与综合产品加氢处理和催化剂级联

    公开(公告)号:US20110042272A1

    公开(公告)日:2011-02-24

    申请号:US12583276

    申请日:2009-08-19

    IPC分类号: C10G1/08 C10G1/06

    摘要: A multi-stage catalytic process for the direct liquefaction of coal is utilized with a hydrotreater to first liquefy and subsequently treat the product in one integrated process. A fresh hydrogenation catalyst is used to reduce heteroatoms (S, N) from coal liquids in the downstream hydrotreater. This catalyst is then cascaded and re-used in the direct coal liquefaction process, first in the low temperature Stage 1, and then re-used in the high temperature Stage 2. Coal liquid products have very low contaminants and can be readily used to produce gasoline and diesel fuel. Catalyst requirements are substantially lowered utilizing this novel process.

    摘要翻译: 用于直接液化煤的多阶段催化方法与加氢处理器一起利用,以首先在一个整合过程中液化并随后处理该产物。 使用新鲜的氢化催化剂从下游加氢处理机中的煤液中还原杂原子(S,N)。 然后将该催化剂级联并在直接煤液化过程中重新使用,首先在低温阶段1中,然后在高温阶段2中重新使用。煤液体产物具有非常低的污染物并且可以容易地用于生产 汽油和柴油燃料。 利用这种新颖的方法,催化剂需求大大降低。

    Broadly tunable single-mode quantum cascade laser sources and sensors
    6.
    发明授权
    Broadly tunable single-mode quantum cascade laser sources and sensors 有权
    广泛可调单模量子级联激光源和传感器

    公开(公告)号:US07826509B2

    公开(公告)日:2010-11-02

    申请号:US11611819

    申请日:2006-12-15

    IPC分类号: H01S5/00 H01S3/10 H01S3/13

    摘要: A broadly tunable single-mode infrared laser source based on semiconductor lasers. The laser source has two parts: an array of closely-spaced DFB QCLs (or other semiconductor lasers) and a controller that can switch each of the individual lasers in the array on and off, set current for each of the lasers and, and control the temperature of the lasers in the array. The device can be used in portable broadband sensors to simultaneously detect a large number of compounds including chemical and biological agents. A microelectronic controller is combined with an array of individually-addressed DFB QCLs with slightly different DFB grating periods fabricated on the same broadband (or multiple wavelengths) QCL material. This allows building a compact source providing narrow-line broadly-tunable coherent radiation in the Infrared or Terahertz spectral range (as well as in the Ultraviolet and Visible spectral ranges, using semiconductor lasers with different active region design). The performance (tuning range, line width, power level) is comparable to that of external grating tunable semiconductor lasers, but the proposed design is much smaller and much easier to manufacture.

    摘要翻译: 基于半导体激光器的广泛可调单模红外激光源。 激光源具有两部分:紧密间隔的DFB QCL(或其他半导体激光器)的阵列和能够切换阵列中的每个激光器的每一个的开关的控制器,为每个激光器设置电流和控制 阵列中的激光器的温度。 该装置可用于便携式宽带传感器中以同时检测大量包括化学和生物试剂在内的化合物。 微电子控制器与在相同宽带(或多波长)QCL材料上制造的具有稍微不同的DFB光栅周期的单独寻址的DFB QCL阵列组合。 这样可以在红外或太赫兹光谱范围(以及使用具有不同有源区域设计的半导体激光器的紫外和可见光谱范围)中构建一个紧凑型源,提供窄线宽可调谐相干辐射。 性能(调谐范围,线宽,功率水平)与外部光栅可调谐半导体激光器的性能相当,但所提出的设计要小得多,制造容易得多。

    Process for upgrading coal pyrolysis oils
    7.
    发明申请
    Process for upgrading coal pyrolysis oils 有权
    煤热解油改质工艺

    公开(公告)号:US20100147743A1

    公开(公告)日:2010-06-17

    申请号:US12316611

    申请日:2008-12-16

    IPC分类号: C10G45/20

    摘要: This invention utilizes a novel method and set of operating conditions to efficiently and economically process a potentially very fouling hydrocarbon feedstock. A multi-stage catalytic process for the upgrading of coal pyrolysis oils is developed. Coal Pyrolysis Oils are highly aromatic, olefinic, unstable, contain objectionable sulfur, nitrogen, and oxygen contaminants, and,may contain coal solids which will plug fixed-bed reactors. The pyrolysis oil is fed with hydrogen to a multi-stage ebullated-bed hydrotreater and hydrocracker containing a hydrogenation or hydrocracking catalyst to first stabilize the feed at low temperature and is then fed to downstream reactor(s) at higher temperatures to further treat and hydrocrack the pyrolysis oils to a more valuable syncrude or to finished distillate products. The relatively high heat of reaction is used to provide the energy necessary to increase the temperature of the subsequent stage thus eliminating the need for additional external heat input. A refined heavy oil product stream is recycled to the fresh feed to minimize feedstock fouling of heat exchangers and feed heaters.

    摘要翻译: 本发明利用新颖的方法和一组操作条件来有效和经济地处理可能非常结垢的烃原料。 开发了用于改进煤热解油的多阶段催化方法。 煤热解油是高度芳香的,烯烃的,不稳定的,含有令人反感的硫,氮和氧污染物,并且可能含有将固定床反应器的煤固体。 将热解油用氢气加入到含有氢化或加氢裂化催化剂的多级沸腾床加氢处理器和加氢裂化器中,以在低温下首先稳定进料,然后在较高温度下进料至下游反应器以进一步处理和加氢裂化 热解油更有价值的syncrude或成品馏出物。 相对较高的反应热用于提供增加后续阶段的温度所需的能量,从而消除了额外的外部热量输入的需要。 精炼的重油产品流被再循环到新鲜饲料中以最小化热交换器和饲料加热器的原料污染。

    Catalytic hydrogenation process utilizing multi-stage ebullated bed reactors
    8.
    发明授权
    Catalytic hydrogenation process utilizing multi-stage ebullated bed reactors 失效
    使用多级沸腾床反应器的催化氢化方法

    公开(公告)号:US06270654B1

    公开(公告)日:2001-08-07

    申请号:US09087181

    申请日:1998-05-29

    IPC分类号: C10G4500

    摘要: A process for catalytic multi-stage hydrogenation of heavy carbonaceous feedstocks using catalytic ebullated bed reactors is operated at selected flow and operating conditions so as to provide improved reactor operations and produce increased yield of lower boiling hydrocarbon liquid and gas products. The disclosed process advantageously takes advantage of an external gas/liquid separation unit associated with the first stage reactor to allow for a more efficient and effective catalytic hydrocracking process. The more efficient process is primarily a result of the increased catalyst loading and lower gas hold-up in the ebullated reactors.

    摘要翻译: 使用催化沸腾床反应器的重碳质原料催化多级氢化的方法在所选择的流动和操作条件下操作,以提供改进的反应器操作并产生较低沸点烃液体和气体产物的产率。 所公开的方法有利地利用与第一级反应器相关联的外部气/液分离单元以允许更有效和有效的催化加氢裂化方法。 更有效的方法主要是催化剂负载增加和沸腾反应器中较低气体滞留的结果。

    Serial programming of instruction codes in different numbers of clock
cycles
    9.
    发明授权
    Serial programming of instruction codes in different numbers of clock cycles 失效
    不同时钟周期的指令代码的串行编程

    公开(公告)号:US5815510A

    公开(公告)日:1998-09-29

    申请号:US624193

    申请日:1996-03-28

    IPC分类号: G01R31/3185 G01R31/28

    摘要: A method for coding programming instructions in a complex programmable logic device (CPLD). In one embodiment, a CPLD has an instruction storage element comprising a first number of bits and requiring a first number of clock cycles to load the first number of bits. A novel method is used to instruct the device to perform at least one function comprising the steps of serially shifting a first instruction into the instruction storage element in a second number of clock cycles, and serially shifting a second instruction into the instruction storage element in a third number of clock cycles. The third number of clock cycles may be less than the first number of clock cycles. The third number of clock cycles may also be less than the second number of clock cycles. In one embodiment, the third number of clock cycles comprises one clock cycle.

    摘要翻译: 一种用于对复杂可编程逻辑器件(CPLD)中的编程指令进行编码的方法。 在一个实施例中,CPLD具有包括第一数量位的指令存储元件,并且需要第一数量的时钟周期来加载第一数量的位。 一种新颖的方法用于指示设备执行至少一个功能,包括以第二数量的时钟周期将第一指令串行地移位到指令存储元件中的步骤,并且将第二指令串行地移位到指令存储元件中 第三个时钟周期数。 第三个时钟周期数可能小于第一个时钟周期数。 第三个时钟周期数也可能小于第二个时钟周期数。 在一个实施例中,第三数量的时钟周期包括一个时钟周期。

    Circuit for high speed serial programming of programmable logic devices
    10.
    发明授权
    Circuit for high speed serial programming of programmable logic devices 失效
    可编程逻辑器件的高速串行编程电路

    公开(公告)号:US5748559A

    公开(公告)日:1998-05-05

    申请号:US587659

    申请日:1996-01-17

    IPC分类号: G11C7/10 G11C8/04 G11C8/00

    CPC分类号: G11C8/04 G11C7/1006

    摘要: The present invention provides a circuit for programming a logic device comprising a first register for shifting data to a memory array, a second register for decoding an address space for a particular word within the logic device. The memory array has an address input and a data input coupled to the first and second registers. One of the registers is implemented as a registered counter block while the other register can be implemented as either a shift register, for a low pin count design, and/or a parallel load register for a higher pin counter and higher performance design.

    摘要翻译: 本发明提供一种用于编程逻辑器件的电路,该逻辑器件包括用于将数据移位到存储器阵列的第一寄存器,用于对逻辑器件内的特定字解码地址空间的第二寄存器。 存储器阵列具有耦合到第一和第二寄存器的地址输入和数据输入。 其中一个寄存器被实现为注册计数器块,而另一个寄存器可以实现为移位寄存器,低引脚数设计和/或用于更高引脚计数器和更高性能设计的并行加载寄存器。