SYSTEM AND METHOD OF DISPLAY DEVICE
    1.
    发明申请
    SYSTEM AND METHOD OF DISPLAY DEVICE 审中-公开
    显示装置的系统和方法

    公开(公告)号:US20140354535A1

    公开(公告)日:2014-12-04

    申请号:US14013027

    申请日:2013-08-28

    IPC分类号: G09G5/00 G09G5/37 G06F3/01

    CPC分类号: G09G5/00 G09G2354/00

    摘要: The invention proposes a system and method of a display device. When the distance between a user and the display device is too close or far, or the angle between the user and the display device slants too much, the display device sends out a command to inform the user to adjust the user's position while watching the display device. A method for the display device comprises following steps: a detecting device and an operating system calculating a relative position between the user and the display device, the operating system generating an warning command according to the relative position, a warning module receiving the warning command and afterward sending out the command, the command being sent to a display module, a motion-generating device and an audio device.

    摘要翻译: 本发明提出了一种显示装置的系统和方法。 当用户和显示设备之间的距离太近或远,或者用户与显示设备之间的角度倾斜太多时,显示设备发出命令以通知用户在观看显示器的同时调整用户的位置 设备。 一种显示装置的方法,包括以下步骤:检测装置和计算用户与显示装置之间的相对位置的操作系统,操作系统根据相对位置生成警告命令,接收警告命令的警告模块和 之后发出命令,该命令被发送到显示模块,运动产生装置和音频装置。

    Allen Wrench Structure
    2.
    发明申请
    Allen Wrench Structure 审中-公开
    艾伦扳手结构

    公开(公告)号:US20160332285A1

    公开(公告)日:2016-11-17

    申请号:US14887432

    申请日:2015-10-20

    申请人: Joun-Jan Chen

    发明人: Joun-Jan Chen

    IPC分类号: B25B15/00 B25B27/18

    CPC分类号: B25B15/008 B25B27/18

    摘要: An Allen wrench structure contains: at least one operating segment formed on a gripping handle and having plural hexagonal cross-sectional faces, wherein the at least one operating segment has a first cross-sectional face and a second cross-sectional face. A diameter L1 of an inscribed circle of the first cross-sectional face is less than a diameter L2 of an inscribed circle of the second cross-sectional face, and a working part of the at least one operation segment between the first cross-sectional face and the second cross-sectional face is conical. A misalignment angle θ1 is defined between the first cross-sectional face and the second cross-sectional face so that among six vertices of the first cross-sectional face and six vertices of the second cross-sectional face are defined six extending edges, and each extending edge is defined between each vertex of the first cross-sectional face and each vertex of the second cross-sectional face.

    摘要翻译: 内六角扳手结构包括:至少一个操作段,其形成在抓握手柄上并且具有多个六边形横截面,其中所述至少一个操作段具有第一横截面和第二横截面。 第一横截面的内切圆的直径L1小于第二截面的内切圆的直径L2,第一横截面的内切圆的工作部分 并且第二横截面为圆锥形。 在第一截面和第二横截面之间限定了不对准角θ1,使得在第一横截面的六个顶点和第二横截面的六个顶点之间限定六个延伸边缘,并且每个 在第一横截面的每个顶点和第二横截面的每个顶点之间限定延伸边缘。

    Apparatus and method for on-chip sampling of dynamic IR voltage drop
    3.
    发明授权
    Apparatus and method for on-chip sampling of dynamic IR voltage drop 有权
    用于片上采样动态IR电压降的装置和方法

    公开(公告)号:US08614571B2

    公开(公告)日:2013-12-24

    申请号:US13299445

    申请日:2011-11-18

    IPC分类号: G01R19/00 G01R27/08

    摘要: Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.

    摘要翻译: 集成电路芯片上的测试点,特别是沿着电源轨的IR电压降的点被耦合到由芯片上所有的自动测试控制器控制的比较器。 每个测试点可以在测试范围内具有一个或多个比较器和一个或多个参考电压。 比较器状态的改变设置在测试间隔期间由片上自动测试控制器读取和复位的锁存器。 自动测试控制器可以在测试期间与外部自动测试设备进行协调,并将激励信号施加到芯片。 测试间隔期间的最大电压降由耦合到最低参考电压的开关比较器的锁存输出确定。 闩锁的设置和复位可以通过可选择的延迟来选通,以便区分持续更长或更短时间的偏移。

    APPARATUS FOR CLOCK SKEW COMPENSATION
    4.
    发明申请
    APPARATUS FOR CLOCK SKEW COMPENSATION 有权
    时钟补偿装置

    公开(公告)号:US20120146693A1

    公开(公告)日:2012-06-14

    申请号:US13114030

    申请日:2011-05-23

    IPC分类号: H03L7/06

    摘要: An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.

    摘要翻译: 提供了一种用于时钟偏移补偿的装置。 该装置包括设置在第一管芯中的第一延迟锁定环(DLL)模块和设置在第二管芯中的第二DLL模块。 第一DLL模块的第一输入端接收参考时钟。 第二DLL模块的第一输入端电连接到第一DLL模块的输出端。 第二DLL模块的输出端电连接到第一DLL模块的第二输入端。

    Selective CESL structure for CMOS application
    6.
    发明授权
    Selective CESL structure for CMOS application 有权
    CMOS应用的选择性CESL结构

    公开(公告)号:US07696578B2

    公开(公告)日:2010-04-13

    申请号:US11349804

    申请日:2006-02-08

    IPC分类号: H01L27/092

    摘要: A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.

    摘要翻译: 提供了较少受负偏压时间不稳定性(NBTI)影响的PMOS器件及其形成方法。 PMOS器件在PMOS器件的栅极结构,栅极间隔物和源极/漏极区域的至少一部分上包括阻挡层。 然后在阻挡层上形成应力层。 阻挡层优选为氧化物层,优选不为NMOS器件形成。

    Compound containing carboxylate ester and N2S2 ligand bi-functional groups and manufacturing method thereof
    7.
    发明申请
    Compound containing carboxylate ester and N2S2 ligand bi-functional groups and manufacturing method thereof 有权
    含羧酸酯和N2S2配位体双官能团的化合物及其制备方法

    公开(公告)号:US20100056804A1

    公开(公告)日:2010-03-04

    申请号:US12203214

    申请日:2008-09-03

    IPC分类号: C07D207/30

    CPC分类号: C07D207/46 Y02P20/55

    摘要: A compound containing carboxylate ester and N2S2 ligand bi-functional groups and a manufacturing method thereof are disclosed. The S in the N2S2 ligand of the compound containing carboxylate ester and N2S2 ligand bi-functional groups includes a protective group so as to avoid to be oxidized and easy storage. In a complex reaction, the protective group is automatically released As to the active carboxylate ester, it is for reacting with compounds having amino groups such as amines, amino acids, peptides, or protein etc while the N2S2 ligand is for bonding with technetium or rhenium so as to form neutral complex. The compound containing carboxylate ester and N2S2 ligand bi-functional groups is applied to radiopharmaceuticals such as contrast agents for tissues and target agents.

    摘要翻译: 公开了含有羧酸酯和N 2 S 2配位体双官能团的化合物及其制备方法。 含有羧酸酯和N2S2配位体双官能团的化合物的N2S2配体中的S包括保护基,以避免被氧化并容易储存。 在复杂的反应中,保护基被自动释放对于活性羧酸酯,它是与具有氨基的化合物如胺,氨基酸,肽或蛋白质等反应,而N2S2配体与锝或铼键合 从而形成中性复合物。 含有羧酸酯和N 2 S 2配位体双功能基团的化合物被应用于放射性药物,例如用于组织和靶标的造影剂。

    Jitter measuring system and method
    8.
    发明申请
    Jitter measuring system and method 有权
    抖动测量系统及方法

    公开(公告)号:US20090088996A1

    公开(公告)日:2009-04-02

    申请号:US12232553

    申请日:2008-09-19

    IPC分类号: G01R29/26

    CPC分类号: G01R31/31709

    摘要: The present invention relates to a jitter measuring system, comprising: a delay circuit for receiving a clock signal and delaying the clock signal to generate a delay signal; a jitter amplifier for receiving the clock signal and delay signal to generate a first signal and a second signal; and a converter for converting a phase different between the first signal and the second signal into a relevant digital code; wherein the phase difference between the first signal and the second signal is an amplification of jitter.

    摘要翻译: 抖动测量系统技术领域本发明涉及抖动测量系统,包括:延迟电路,用于接收时钟信号并延迟时钟信号以产生延迟信号; 抖动放大器,用于接收时钟信号和延迟信号以产生第一信号和第二信号; 以及转换器,用于将第一信号和第二信号之间的相位转换成相关的数字码; 其中第一信号和第二信号之间的相位差是抖动的放大。

    METHOD FOR PRE-CALIBRATING BALANCE GAIN OF ANALOG FRONT END IN OPTICAL DISK DRIVE TO CALIBRATE VARIATION OF FOCUS BALANCE
    9.
    发明申请
    METHOD FOR PRE-CALIBRATING BALANCE GAIN OF ANALOG FRONT END IN OPTICAL DISK DRIVE TO CALIBRATE VARIATION OF FOCUS BALANCE 失效
    用于在光盘驱动器中预先校准模拟前端的平衡校正方法用于校准焦距平衡变化的方法

    公开(公告)号:US20080225655A1

    公开(公告)日:2008-09-18

    申请号:US12047788

    申请日:2008-03-13

    申请人: Der Jan CHEN

    发明人: Der Jan CHEN

    IPC分类号: G11B7/00

    CPC分类号: G11B7/0945

    摘要: A method for pre-calibrating a balance gain of an analog front end in an optical disk drive to calibrate a variation of a focus balance. The method includes the steps of: adjusting the balance gain of the focus balance; moving a lens and getting an S curve; and comparing a positive half cycle of the S curve with a negative half cycle of the S curve. When the positive half cycle is equal to the negative half cycle, it represents that the balance gain of the focus balance is optimized and the procedure ends; or otherwise the above-mentioned steps are repeated to adjust the balance gain of the focus balance again. Because the balance gain is pre-calibrated, the optimal power calibration, the successful disk-reading possibility, the write-in quality and the stability of the disk judging mechanism can be enhanced and the consistency and the stability of the product can be improved.

    摘要翻译: 一种用于预校准光盘驱动器中的模拟前端的平衡增益以校准焦距平衡的变化的方法。 该方法包括以下步骤:调整焦距平衡的平衡增益; 移动镜头并获得S曲线; 并将S曲线的正半周期与S曲线的负半周进行比较。 当正半周期等于负半周期时,表示焦距平衡的平衡增益得到优化,程序结束; 否则重复上述步骤以再次调整焦距平衡的平衡增益。 由于平衡增益是预校准的,所以可以提高最佳的功率校准,成功的磁盘读取可能性,写入质量和磁盘判断机制的稳定性,从而提高产品的一致性和稳定性。

    Bias circuits and signal amplifier circuits
    10.
    发明申请
    Bias circuits and signal amplifier circuits 有权
    偏置电路和信号放大器电路

    公开(公告)号:US20080143444A1

    公开(公告)日:2008-06-19

    申请号:US11808678

    申请日:2007-06-12

    IPC分类号: H03F3/04

    CPC分类号: H03F1/0266 H03F1/0288

    摘要: A bias circuit includes a transistor having a control gate, a first terminal and a second terminal coupled to a ground level, a first resistor coupled to the control gate, a first capacitor coupled between an input signal and the first resistor, a diode coupled between a connection point of the first capacitor and the first resistor, and the ground level, a second capacitor coupled between the control gate and the ground level, a second resistor coupled between the control gate and the ground level, a third resistor coupled between the control gate and a predetermined voltage, a fourth resistor coupled between the predetermined voltage and the first terminal, and a fifth resistor coupled between the first terminal and a bias signal. A current through the transistor corresponds to the input signal, and the bias signal is generated according to the current through the transistor.

    摘要翻译: 偏置电路包括具有控制栅极,耦合到地电平的第一端子和第二端子的晶体管,耦合到控制栅极的第一电阻器,耦合在输入信号和第一电阻器之间的第一电容器, 第一电容器和第一电阻器的连接点和地电平,耦合在控制栅极和地电平之间的第二电容器,耦合在控制栅极和地电平之间的第二电阻器,耦合在控制栅极和地电平之间的第三电阻器, 栅极和预定电压,耦合在预定电压和第一端子之间的第四电阻器,以及耦合在第一端子和偏置信号之间的第五电阻器。 通过晶体管的电流对应于输入信号,并且根据通过晶体管的电流产生偏置信号。