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    SELF-ALIGNED ARRAY CONTACT FOR MEMORY CELLS
    1.
    发明申请
    SELF-ALIGNED ARRAY CONTACT FOR MEMORY CELLS 失效
    自定义阵列与记忆体的联系

    公开(公告)号：US20050077562A1

    公开(公告)日：2005-04-14

    申请号：US10605590

    申请日：2003-10-10

    申请人： Rama Divakaruni ,  Johnathan Faltermeier ,  Michael Maldei ,  Jay Strane

    发明人： Rama Divakaruni ,  Johnathan Faltermeier ,  Michael Maldei ,  Jay Strane

    IPC分类号： H01L21/60 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L21/76897 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

    摘要： A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

    摘要翻译： 提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。 该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。 在槽中形成与基板和位线的位线接触。 此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管 在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。

    Self-aligned array contact for memory cells
    4.
    发明授权
    Self-aligned array contact for memory cells 失效
    用于存储单元的自对准阵列触点

    公开(公告)号：US06870211B1

    公开(公告)日：2005-03-22

    申请号：US10605590

    申请日：2003-10-10

    申请人： Rama Divakaruni ,  Johnathan E. Faltermeier ,  Michael Maldei ,  Jay Strane

    发明人： Rama Divakaruni ,  Johnathan E. Faltermeier ,  Michael Maldei ,  Jay Strane

    IPC分类号： H01L21/60 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L21/76897 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

    摘要： A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

    摘要翻译： 提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。 该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。 在槽中形成与基板和位线的位线接触。 此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管 在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。

    Pitcher-shaped active area for field effect transistor and method of forming same
    6.
    发明授权
    Pitcher-shaped active area for field effect transistor and method of forming same 失效
    投币型场效应晶体管及其形成方法

    公开(公告)号：US06960514B2

    公开(公告)日：2005-11-01

    申请号：US10803395

    申请日：2004-03-18

    申请人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

    发明人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224

    摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

    摘要翻译： 对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。 投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。 还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部 区域结构。 本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

    Nitrided STI liner oxide for reduced corner device impact on vertical device performance
    9.
    发明授权
    Nitrided STI liner oxide for reduced corner device impact on vertical device performance 有权
    氮化氮化物衬垫氧化物，用于减少拐角装置对垂直装置性能的影响

    公开(公告)号：US06998666B2

    公开(公告)日：2006-02-14

    申请号：US10707754

    申请日：2004-01-09

    申请人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

    发明人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10894

    摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.

    摘要翻译： 一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极 导体和掺硼通道。 该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。 然后在DRAM单元的两侧的沟槽中形成隔离区。 此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。 与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。

    STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR
    10.
    发明申请
    STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR 有权
    带有收集器的自对准双极晶体管的结构和方法

    公开(公告)号：US20050184359A1

    公开(公告)日：2005-08-25

    申请号：US10708340

    申请日：2004-02-25

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

    IPC分类号： H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/737

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

    摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

    摘要翻译： 提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积 下表面。 双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。 在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。