公开(公告)号：US09231549B2

公开(公告)日：2016-01-05

申请号：US13380511

申请日：2009-08-10

Applicant: Ming-Da Tsai ,  Jing-Hong Conan Zhan ,  Arun Natarajan

Inventor： Ming-Da Tsai ,  Jing-Hong Conan Zhan ,  Arun Natarajan

IPC: H01P1/18 ,  H03H7/20

CPC classification number: H03H7/20

Abstract: A phase shifter and related load device are provided. The phase shifter includes a phase shifter core and load devices. The phase shifter core has an input port for receiving an input signal, an output port for outputting an output signal, and connection ports. The load devices are coupled to the connection ports, respectively. At least one of the load devices includes first varactor units each having a first node and a second node, where first nodes of the first varactor units are coupled to a first voltage, second nodes of the first varactor units are respectively coupled to a plurality of second voltages, and the second voltages include at least two voltages different from each other. The phase shifter and related load device are capable of mitigating effects resulted from varactor's non-linear C-V curve.

Abstract translation: 提供了一种移相器和相关负载装置。 移相器包括移相器核和负载装置。 移相器核具有用于接收输入信号的输入端口，用于输出输出信号的输出端口和连接端口。 负载设备分别耦合到连接端口。 负载装置中的至少一个包括第一变容二极管单元，每个变容二极管单元具有第一节点和第二节点，其中第一变容二极管单元的第一节点耦合到第一电压，第一变容二极管单元的第二节点分别耦合到多个 第二电压，第二电压包括彼此不同的至少两个电压。 移相器和相关的负载装置能够减轻变容二极管非线性C-V曲线产生的影响。

公开(公告)号：US20150143837A1

公开(公告)日：2015-05-28

申请号：US14347734

申请日：2012-09-13

Applicant: Lisheng Zhang ,  Benhe Dou ,  Jing Hong

Inventor： Lisheng Zhang ,  Benhe Dou ,  Jing Hong

IPC: F25C5/00 ,  F25D23/12

CPC classification number: F25D23/12 ,  F25C5/22 ,  F25C2500/06

Abstract: A cooling appliance (100) is provided, including a heat insulation cabinet (10), in which a storage chamber is formed; and a door (11), which cooperates with the heat insulation cabinet (10) to selectively open or close the storage chamber. The cooling appliance (100) further includes an dispenser system (20) capable of allocating ice and liquid, where the dispenser system (20) is used for allocating ice in an ice storage container of the cooling appliance (100) into an dispenser cavity (21). The dispenser system (20) includes an ice channel (40) and a splash-proof component (30), where the splash-proof component (30) includes a buffering part, so as to be used for absorbing at least one part of kinetic energy of ice when the ice passes through, to reduce spreading and splashing of the ice.

Abstract translation: 提供了一种冷却设备（100），包括：隔热柜（10），其中形成有储存室; 以及与隔热柜（10）配合以选择性地打开或关闭储存室的门（11）。 冷却设备（100）还包括能够分配冰和液体的分配器系统（20），其中分配器系统（20）用于将冷却设备（100）的储冰容器中的冰分配到分配器空腔（ 21）。 分配器系统（20）包括冰通道（40）和防溅部件（30），其中防溅部件（30）包括缓冲部件，以便用于吸收至少一部分动力学 冰通过时的冰的能量，以减少冰的扩散和飞溅。

公开(公告)号：US08941448B2

公开(公告)日：2015-01-27

申请号：US13272802

申请日：2011-10-13

Applicant: Tiku Yu ,  Jing-Hong Conan Zhan

Inventor： Tiku Yu ,  Jing-Hong Conan Zhan

IPC: H01P5/12 ,  H01P5/16 ,  H03H7/18

CPC classification number: H01P5/16

Abstract: An M-way coupler having a first port, M second ports, M transmission line sections, M isolation resistors and a phase shifting network is disclosed, where M is an integer number greater than 1. The M transmission line sections couple the first port to the M second ports, respectively. Each of the M isolation resistors has a first terminal and a second terminal. The first terminals of the M isolation resistors are coupled to the M second ports, respectively. The phase shifting network has M I/O terminals coupled to the second terminals of the M isolation resistors, respectively. The phase shifting network is arranged to provide a phase shift within a predetermined tolerance margin between arbitrary two I/O terminals of the M I/O terminals of the phase shifting network.

Abstract translation: 公开了具有第一端口，M个第二端口，M个传输线路段，M个隔离电阻器和一个移相网络的M路耦合器，其中M是大于1的整数.M个传输线段将第一端口耦合到 M个第二个端口。 每个M个隔离电阻具有第一端子和第二端子。 M个隔离电阻器的第一个端子分别耦合到M个第二端口。 相移网络具有分别耦合到M个隔离电阻器的第二端子的M I / O端子。 相移网络被布置成在相移网络的M I / O端子的任意两个I / O端子之间提供预定容限裕度内的相移。

公开(公告)号：US08791732B2

公开(公告)日：2014-07-29

申请号：US13291498

申请日：2011-11-08

Applicant: Jui-Lin Hsu ,  Chih-Hsien Shen ,  Chunwei Chang ,  Jing-Hong Conan Zhan

Inventor： Jui-Lin Hsu ,  Chih-Hsien Shen ,  Chunwei Chang ,  Jing-Hong Conan Zhan

IPC: H03L7/06

CPC classification number: H01L23/5225 ,  H01L23/5227 ,  H01L2924/0002 ,  H03L7/093 ,  H01L2924/00

Abstract: A phase locked loop is provided. The phase locked loop includes a detector, a controlled oscillator and a filtering unit coupled between the detector and the controlled oscillator. The detector generates a phase difference signal according to a reference frequency and an oscillation signal. The controlled oscillator generates the oscillation signal according to a filtered signal. The filtering unit filters the phase difference signal to generate the filtered signal, and the filtering unit has a high frequency filter of which a pole is greater than the reference frequency and less than a frequency of the oscillation signal.

Abstract translation: 提供锁相环。 锁相环包括耦合在检测器和受控振荡器之间的检测器，受控振荡器和滤波单元。 检测器根据参考频率和振荡信号产生相位差信号。 受控振荡器根据滤波信号产生振荡信号。 滤波单元对相位差信号进行滤波以生成滤波信号，滤波单元具有高于基准频率的极点并且小于振荡信号的频率的高频滤波器。

公开(公告)号：US20130200922A1

公开(公告)日：2013-08-08

申请号：US13548079

申请日：2012-07-12

Applicant: Yu-Li HSUEH ,  Jing-Hong Conan ZHAN

Inventor： Yu-Li HSUEH ,  Jing-Hong Conan ZHAN

IPC: H03L7/089

CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L7/0896 ,  H03L7/1072

Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.

Abstract translation: 本发明提供了一种解决方案，通过各种电路配置通过各种电路配置升级相位频率检测器（PFD）和电荷泵（CP）增益，提供令人满意的性能，而不需要锁相环（PLL）电路的显着占地面积， 采用一个或多个触发器，延迟元件和高级电路技术。

公开(公告)号：US08319532B2

公开(公告)日：2012-11-27

申请号：US13097050

申请日：2011-04-28

Applicant: Yu-Li Hsueh ,  Jing-Hong Conan Zhan

Inventor： Yu-Li Hsueh ,  Jing-Hong Conan Zhan

IPC: H03K21/00

CPC classification number: H03L7/18 ,  H03K21/026

Abstract: A frequency divider comprises a phase selector and a timing circuit. The phase selector is arranged to receive a plurality of input signals and a plurality of control signals and output a plurality of output signals according to the control signals, wherein a predetermined reference voltage and the input signals are selectively chosen to generate the output signals according to the control signals, and the input signals are of a same frequency but different phases. The timing circuit is arranged to receive the output signals and generate the control signals according to the output signals.

Abstract translation: 分频器包括相位选择器和定时电路。 相位选择器被布置成根据控制信号接收多个输入信号和多个控制信号并输出​​多个输出信号，其中选择性地选择预定参考电压和输入信号以根据 控制信号和输入信号具有相同的频率但不同的相位。 定时电路被配置为接收输出信号并根据输出信号产生控制信号。

公开(公告)号：US20120293362A1

公开(公告)日：2012-11-22

申请号：US13473567

申请日：2012-05-16

Applicant: Chuan-Kang Liang ,  Jing-Hong Conan Zhan ,  Ti-Ku Yu ,  Zhiming Deng

Inventor： Chuan-Kang Liang ,  Jing-Hong Conan Zhan ,  Ti-Ku Yu ,  Zhiming Deng

IPC: G01S7/40 ,  H01Q3/00

CPC classification number: H01Q3/267 ,  H01Q3/2605

Abstract: A phase-arrayed device includes: a signal processing circuit arranged to generate a specific signal; a first phase-arrayed channel arranged to provide a first phase-arrayed signal according to the specific signal; a first conducting path arranged to conduct the specific signal to the first phase-arrayed channel; a second conducting path arranged to conduct the first phase-arrayed signal to the signal processing circuit; and a detecting circuit, arranged to detect a mismatch between the first phase-arrayed signal and a reference signal to generate a detecting signal utilized for calibrating the first phase-arrayed signal.

Abstract translation: 相位阵列器件包括：信号处理电路，被配置为产生特定信号; 布置成根据特定信号提供第一相位阵列信号的第一相位阵列信道; 布置成将特定信号传导到第一相位阵列信道的第一导电路径; 第二导电路径，布置成将第一相位阵列信号传导到信号处理电路; 以及检测电路，被配置为检测第一相位阵列信号与参考信号之间的失配，以产生用于校准第一相位阵列信号的检测信号。

公开(公告)号：US20120286834A1

公开(公告)日：2012-11-15

申请号：US13291498

申请日：2011-11-08

Applicant: Jui-Lin Hsu ,  Chih-Hsien Shen ,  Chunwei Chang ,  Jing-Hong Conan Zhan

Inventor： Jui-Lin Hsu ,  Chih-Hsien Shen ,  Chunwei Chang ,  Jing-Hong Conan Zhan

IPC: H03L7/08

CPC classification number: H01L23/5225 ,  H01L23/5227 ,  H01L2924/0002 ,  H03L7/093 ,  H01L2924/00

Abstract: A phase locked loop is provided. The phase locked loop includes a detector, a controlled oscillator and a filtering unit coupled between the detector and the controlled oscillator. The detector generates a phase difference signal according to a reference frequency and an oscillation signal. The controlled oscillator generates the oscillation signal according to a filtered signal. The filtering unit filters the phase difference signal to generate the filtered signal, and the filtering unit has a high frequency filter of which a pole is greater than the reference frequency and less than a frequency of the oscillation signal.

Abstract translation: 提供锁相环。 锁相环包括耦合在检测器和受控振荡器之间的检测器，受控振荡器和滤波单元。 检测器根据参考频率和振荡信号产生相位差信号。 受控振荡器根据滤波信号产生振荡信号。 滤波单元对相位差信号进行滤波以生成滤波信号，滤波单元具有高于基准频率的极点并且小于振荡信号的频率的高频滤波器。

公开(公告)号：US20120105172A1

公开(公告)日：2012-05-03

申请号：US13380511

申请日：2009-08-10

Applicant: Ming-Da Tsai ,  Jing-Hong Conan Zhan ,  Arun Natarajan

Inventor： Ming-Da Tsai ,  Jing-Hong Conan Zhan ,  Arun Natarajan

IPC: H01P1/18 ,  H03H7/20

CPC classification number: H03H7/20

Abstract: A phase shifter and related load device are provided. The phase shifter includes a phase shifter core and load devices. The phase shifter core has an input port for receiving an input signal, an output port for outputting an output signal, and connection ports. The load devices are coupled to the connection ports, respectively. At least one of the load devices includes first varactor units each having a first node and a second node, where first nodes of the first varactor units are coupled to a first voltage, second nodes of the first varactor units are respectively coupled to a plurality of second voltages, and the second voltages include at least two voltages different from each other. The phase shifter and related load device are capable of mitigating effects resulted from varactor's non-linear C-V curve.

Abstract translation: 提供了一种移相器和相关负载装置。 移相器包括移相器核和负载装置。 移相器核具有用于接收输入信号的输入端口，用于输出输出信号的输出端口和连接端口。 负载装置分别耦合到连接端口。 负载装置中的至少一个包括第一变容二极管单元，每个变容二极管单元具有第一节点和第二节点，其中第一变容二极管单元的第一节点耦合到第一电压，第一变容二极管单元的第二节点分别耦合到多个 第二电压，第二电压包括彼此不同的至少两个电压。 移相器和相关的负载装置能够减轻变容二极管非线性C-V曲线产生的影响。

公开(公告)号：US07791428B2

公开(公告)日：2010-09-07

申请号：US12235615

申请日：2008-09-23

Applicant: Hsiang-Hui Chang ,  Ping-Ying Wang ,  Jing-Hong Conan Zhan ,  Bing-Yu Hsieh

Inventor： Hsiang-Hui Chang ,  Ping-Ying Wang ,  Jing-Hong Conan Zhan ,  Bing-Yu Hsieh

IPC: H03C3/02 ,  H03C3/08

CPC classification number: H03L7/085 ,  H03L7/0991 ,  H03L2207/50

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract translation: 为了减少模拟锁相环中的误差，使用具有数字组件和数字操作的全数字锁相环（ADPLL）。 ADPLL也可用于直接调频（DFM）。 通过将ADPLL的比例路径增益定义为ADPLL的带宽和参考频率，通过TDC增益，DCO增益，分频器的分频比，放大器的增益或其组合，增益 可以调整放大器，使得可以良好校准ADPLL的最佳环路带宽。 为了达到ADPLL完全数字化的目的，TDC和DCO的收益可能会以数字方式进一步调整。