公开(公告)号：US07132739B2

公开(公告)日：2006-11-07

申请号：US10975839

申请日：2004-10-28

申请人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

发明人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

IPC分类号： H01L23/31

CPC分类号： H01L23/544 ,  H01L21/565 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06593

摘要： Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

摘要翻译： 描述了用于封装半导体管芯堆叠的系统和方法。 可以形成半导体管芯堆叠，例如通过将管芯连接到附接到框架上的柔性印刷电路支架并堆叠支撑件，然后通过使液体密封剂流过骰子堆叠并固化液体密封剂来进行封装。 管芯支撑件可以包含允许液体密封剂围绕骰子堆流动的密封剂流动开口，例如矩形狭缝。

公开(公告)号：US20050085034A1

公开(公告)日：2005-04-21

申请号：US10975839

申请日：2004-10-28

申请人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

发明人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

IPC分类号： H01L21/56 ,  H01L21/8238 ,  H01L21/98 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065 ,  H01L29/74

CPC分类号： H01L23/544 ,  H01L21/565 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06593

摘要： Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

摘要翻译： 描述了用于封装半导体管芯堆叠的系统和方法。 可以形成半导体管芯堆叠，例如通过将管芯连接到附接到框架上的柔性印刷电路支架并堆叠支撑件，然后通过使液体密封剂流过骰子堆叠并固化液体密封剂来进行封装。 管芯支撑件可以包含允许液体密封剂围绕骰子堆流动的密封剂流动开口，例如矩形狭缝。

公开(公告)号：US20120112336A1

公开(公告)日：2012-05-10

申请号：US12940446

申请日：2010-11-05

申请人： John S. Guzek ,  Robert L. Sankman ,  Kinya Ichikawa ,  Yoshihiro Tomita ,  Jiro Kubota

发明人： John S. Guzek ,  Robert L. Sankman ,  Kinya Ichikawa ,  Yoshihiro Tomita ,  Jiro Kubota

IPC分类号： H01L23/528 ,  H01L21/48

CPC分类号： H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

摘要： An encapsulated die (100, 401) comprises a substrate (110, 510) having a first surface (111), an opposing second surface (112), and intervening side surfaces (113), with active devices located at the first surface of the substrate. The active devices are connected by a plurality of electrically conductive layers (120, 520) that are separated from each other by a plurality of electrically insulating layers (125, 525). A protective cap (130, 530) is located over the first surface of the substrate contains an interconnect structure (140) exposed at a surface (131) thereof. In another embodiment, a microelectronic package (200) comprises a package substrate (250) with an encapsulated die (100) such as was described above embedded therein.

摘要翻译： 封装的管芯（100,401）包括具有第一表面（111），相对的第二表面（112）和中间的侧表面（113）的衬底（110,510），其中有源器件位于第一表面 基质。 有源器件通过由多个电绝缘层（125,525）彼此分离的多个导电层（120,520）连接。 保护盖（130,530）位于衬底的第一表面之上，包含暴露在其表面（131）处的互连结构（140）。 在另一个实施例中，微电子封装（200）包括具有如上所述的封装管芯（100）的封装衬底（250）。

公开(公告)号：US06495397B2

公开(公告)日：2002-12-17

申请号：US09821331

申请日：2001-03-28

申请人： Jiro Kubota ,  Kenji Takahashi

发明人： Jiro Kubota ,  Kenji Takahashi

IPC分类号： H01L2144

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/1607 ,  H01L2224/75252 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15312 ,  H05K3/24 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2203/0195 ,  Y02P70/613 ,  Y10T29/49144 ,  H01L2924/00

摘要： A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. Metal caps comprised of a noble metal such as palladium is applied to the surface of the metal bumps to prevent the metal bumps (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

摘要翻译： 描述了一种连接芯片和基板的倒装芯片方法。 使用热压接合器来对准芯片和衬底并施加接触力以将衬底上的焊料凸块保持在芯片上的金属凸块上。 芯片通过焊接机头部的脉冲加热器从其非本机侧快速加热，直到达到焊料凸块的再流动温度。 近似达到焊料凸点处的回流温度时，接触力被释放。 焊料被保持在其再流动温度以上几秒钟以便于衬底的金属突起和接合的润湿。 由贵金属如钯构成的金属盖被施加到金属凸块的表面，以防止金属凸块（其通常包括高导电性和高反应性金属如铜）在刚好在高温下的高温下氧化 并在重新流动操作期间。

公开(公告)号：US6030854A

公开(公告)日：2000-02-29

申请号：US111268

申请日：1998-07-06

申请人： Yohko Mashimoto ,  Shuji Inoue ,  Jiro Kubota ,  Mashahiro Kuroda

发明人： Yohko Mashimoto ,  Shuji Inoue ,  Jiro Kubota ,  Mashahiro Kuroda

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/48

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L24/75 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3511

摘要： An apparatus and method for forming solder interconnection structures that reduce thermo-mechanical stresses at the solder joints of a semiconductor device and its supporting substrate. In one embodiment, the solder interconnection structure of the present invention comprises a semiconductor device and a substrate having a plurality of solder connections extending from the substrate to electrodes or bond pads on the semiconductor device. A multilayer structure is disposed between the semiconductor device and substrate filling the gap formed by the solder connections. The multilayer structure includes a first layer and a second layer, each having a different coefficient of thermal expansion. Thus, in accordance with the present invention, the stress concentration points are moved away from the solder joints of the semiconductor device and substrate to a point located between the first and second layers of the filler structure.

摘要翻译： 一种用于形成焊接互连结构的装置和方法，其减少半导体器件及其支撑衬底的焊点处的热机械应力。 在一个实施例中，本发明的焊料互连结构包括半导体器件和具有从衬底延伸到半导体器件上的电极或接合焊盘的多个焊接连接的衬底。 在半导体器件和填充由焊料连接形成的间隙的衬底之间设置多层结构。 多层结构包括第一层和第二层，每层具有不同的热膨胀系数。 因此，根据本发明，应力集中点从半导体器件和衬底的焊接点移动到位于填料结构的第一和第二层之间的点。

公开(公告)号：US07132311B2

公开(公告)日：2006-11-07

申请号：US10206007

申请日：2002-07-26

申请人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

发明人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

IPC分类号： H01L21/56

CPC分类号： H01L23/544 ,  H01L21/565 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06593

摘要： Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

摘要翻译： 描述了用于封装半导体管芯堆叠的系统和方法。 可以形成半导体管芯堆叠，例如通过将管芯连接到附接到框架上的柔性印刷电路支架并堆叠支撑件，然后通过使液体密封剂流过骰子堆叠并固化液体密封剂来进行封装。 管芯支撑件可以包含允许液体密封剂围绕骰子堆流动的密封剂流动开口，例如矩形狭缝。

公开(公告)号：US5880530A

公开(公告)日：1999-03-09

申请号：US625797

申请日：1996-03-29

申请人： Yohko Mashimoto ,  Shuji Inoue ,  Jiro Kubota ,  Mashahiro Kuroda

发明人： Yohko Mashimoto ,  Shuji Inoue ,  Jiro Kubota ,  Mashahiro Kuroda

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/48 ,  H01L23/29 ,  H01L23/52

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L24/75 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3511

摘要： An apparatus and method for forming solder interconnection structures that reduce thermo-mechanical stresses at the solder joints of a semiconductor device and its supporting substrate. In one embodiment, the solder interconnection structure of the present invention comprises a semiconductor device and a substrate having a plurality of solder connections extending from the substrate to electrodes or bond pads on the semiconductor device. A multilayer structure is disposed between the semiconductor device and substrate filling the gap formed by the solder connections. The multilayer structure includes a first layer and a second layer, each having a different coefficient of thermal expansion. Thus, in accordance with the present invention, the stress concentration points are moved away from the solder joints of the semiconductor device and substrate to a point located between the first and second layers of the filler structure.

摘要翻译： 一种用于形成焊接互连结构的装置和方法，其减少半导体器件及其支撑衬底的焊点处的热机械应力。 在一个实施例中，本发明的焊料互连结构包括半导体器件和具有从衬底延伸到半导体器件上的电极或接合焊盘的多个焊接连接的衬底。 在半导体器件和填充由焊料连接形成的间隙的衬底之间设置多层结构。 多层结构包括第一层和第二层，每层具有不同的热膨胀系数。 因此，根据本发明，应力集中点从半导体器件和衬底的焊接点移动到位于填料结构的第一和第二层之间的点。