公开(公告)号：US08168318B2

公开(公告)日：2012-05-01

申请号：US12257049

申请日：2008-10-23

申请人： Byung Sung Kwak ,  Nety M. Krishna ,  Kurt Eisenbeiser ,  William J. Dauksher ,  Jon Candelaria

发明人： Byung Sung Kwak ,  Nety M. Krishna ,  Kurt Eisenbeiser ,  William J. Dauksher ,  Jon Candelaria

IPC分类号： H01M6/16 ,  H01M6/18 ,  H01M6/46

CPC分类号： H01M10/0585 ,  H01M6/40 ,  H01M10/0436 ,  H01M10/052 ,  H01M2300/0068

摘要： Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.

摘要翻译： 提供了概念和方法，以通过消除和/或最小化常规物理（阴影）掩模的使用来降低薄膜电池（TFB）大批量制造的成本和复杂性。 激光划线和其他可选的物理无掩模图案化技术满足某些或所有图案化要求。 在一个实施例中，制造薄膜电池的方法包括提供衬底，在衬底上沉积与薄膜电池结构相对应的层，所述层按沉积顺序包括阴极，电解质和阳极，其中至少 沉积层中的一个在沉积期间由物理掩模未图案化，沉积保护涂层，以及划刻层和保护涂层。 此外，层的边缘可以被封装层覆盖。 此外，可以将这些层沉积在两个基板上，然后层压以形成薄膜电池。

公开(公告)号：US4446194A

公开(公告)日：1984-05-01

申请号：US391047

申请日：1982-06-21

申请人： Jon Candelaria ,  Kurt S. Heidinger

发明人： Jon Candelaria ,  Kurt S. Heidinger

IPC分类号： B32B9/00 ,  H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  B05D3/14

CPC分类号： H01L23/5329 ,  H01L2924/0002 ,  H01L2924/09701

摘要： When multilayer-metal electronic devices are heated, voids can form in the metal layers. Void formation is avoided by using a double dielectric layer as the interlayer dielectric. The double layer has a first oxide layer portion in contact with the first metal which is formed by plasma assisted chemical vapor deposition, and a second oxide layer portion formed by other means. The plasma formed oxide layer portion is believed to be in compressive stress relative to the substrate.

摘要翻译： 当多层金属电子器件被加热时，可以在金属层中形成空隙。 通过使用双电介质层作为层间电介质来避免空隙形成。 双层具有与通过等离子体辅助化学气相沉积形成的第一金属接触的第一氧化物层部分和通过其它方式形成的第二氧化物层部分。 认为等离子体形成的氧化物层部分相对于衬底具有压缩应力。

公开(公告)号：US20120214047A1

公开(公告)日：2012-08-23

申请号：US13461286

申请日：2012-05-01

申请人： BYUNG SUNG KWAK ,  Nety M. Krishna ,  Kurt Eisenbeiser ,  William J. Dauksher ,  Jon Candelaria

发明人： BYUNG SUNG KWAK ,  Nety M. Krishna ,  Kurt Eisenbeiser ,  William J. Dauksher ,  Jon Candelaria

IPC分类号： H01M4/70 ,  H01M2/02

CPC分类号： H01M10/0585 ,  H01M6/40 ,  H01M10/0436 ,  H01M10/052 ,  H01M2300/0068

摘要： Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.

摘要翻译： 提供了概念和方法，以通过消除和/或最小化常规物理（阴影）掩模的使用来降低薄膜电池（TFB）大批量制造的成本和复杂性。 激光划线和其他可选的物理无掩模图案化技术满足某些或所有图案化要求。 在一个实施例中，制造薄膜电池的方法包括提供衬底，在衬底上沉积与薄膜电池结构相对应的层，所述层按沉积顺序包括阴极，电解质和阳极，其中至少 沉积层中的一个在沉积期间由物理掩模未图案化，沉积保护涂层，以及划刻层和保护涂层。 此外，层的边缘可以被封装层覆盖。 此外，可以将这些层沉积在两个基板上，然后层压以形成薄膜电池。

公开(公告)号：US20060043438A1

公开(公告)日：2006-03-02

申请号：US10929135

申请日：2004-08-26

申请人： Paige Holm ,  Jon Candelaria

发明人： Paige Holm ,  Jon Candelaria

IPC分类号： H01L31/062

CPC分类号： H01L27/14634 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2924/0002 ,  H01L2924/00

摘要： An exemplary system and method for providing an integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS host wafer (460) bonded with a monocrystalline, optically active donor wafer (300); a photosensing element (390) integrated in said optically active donor wafer (300) having an interconnect via (505, 495, 485) substantially decoupled from the photosensing element (390), wherein the host (460) and donor (300) wafers are bonded through the optically active material in a region disposed near a metalization surface (450, 455, 445) of the CMOS layer (460) in order to allow fabrication of the interconnect (505, 495, 485). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated photosensing components that may be readily incorporated with existing technologies for the improvement of CMOS imaging, device package form factors, weights and/or other manufacturing, device or material performance metrics.

摘要翻译： 公开了一种用于提供适合于在CMOS成像应用中使用的集成光敏元件的示例性系统和方法，其特别包括：与单晶光学活性施主晶片（300）接合的经处理的CMOS主晶片（460）; 集成在所述光学活性施主晶片（300）中的光敏元件（390）具有与光敏元件（390）基本上分离的互连通孔（505,495,485），其中主体（460）和供体（300）晶片是 通过光学活性材料在设置在CMOS层（460）的金属化表面（450,455,445）附近的区域中，以便制造互连（505,495,485）。 公开的特征和规格可以被不同地控制，配置，适配或以其他方式任意地修改，以进一步改善或以其它方式优化光敏性能或其它材料特性。 本发明的示例性实施例代表性地提供了可以容易地与现有技术结合以用于改进CMOS成像，设备封装外形，重量和/或其它制造，器件或材料性能度量的集成光敏元件。

公开(公告)号：US20050040316A1

公开(公告)日：2005-02-24

申请号：US10641216

申请日：2003-08-13

申请人： Paige Holm ,  Jon Candelaria

发明人： Paige Holm ,  Jon Candelaria

IPC分类号： H01L27/00 ,  H01L27/146

CPC分类号： H01L27/14601 ,  H01L27/14636 ,  H01L27/14643

摘要： An exemplary system and method for providing a vertically integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS layer (420); and a photosensing element (380) fabricated in a vertically integrated optically active layer (320, 350), where the optically active layer (320, 350) is bonded to the CMOS layer (420) and the optically active layer (320, 350) is positioned near a metalization surface (405) of the CMOS layer (420). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated photosensing components that may be readily incorporated with existing technologies for the improvement of CMOS imaging, device package form factors, weights and/or other manufacturing, device or material performance metrics.

公开(公告)号：US6049114A

公开(公告)日：2000-04-11

申请号：US118877

申请日：1998-07-20

申请人： Bikas Maiti ,  Jon Candelaria ,  Jian Chen

发明人： Bikas Maiti ,  Jon Candelaria ,  Jian Chen

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6656 ,  H01L21/26586 ,  H01L29/1083 ,  Y10S257/90

摘要： A method of forming a semiconductor device includes providing a substrate (10) and depositing a gate dielectric (12) overlying the substrate (10). A gate is formed overlying the gate dielectric (12). The gate has a first sidewall and comprises a metal-containing layer (14) overlying the gate dielectric (12). A first spacer layer (20) is deposited over the gate and the substrate (10). A portion of the first spacer layer along the first sidewall forms a first spacer (22). A liner layer (30) is deposited over the gate and the substrate (10), and a second spacer layer (32) is deposited over the liner layer (30). The second spacer layer (32) is etched to leave a portion of the second spacer layer (32) along the first sidewall to form a second spacer (34). Also disclosed is a metal gate structure of a semiconductor device.

摘要翻译： 形成半导体器件的方法包括提供衬底（10）并沉积覆盖衬底（10）的栅极电介质（12）。 形成栅极覆盖栅极电介质（12）。 栅极具有第一侧壁并且包括覆盖栅极电介质（12）的含金属层（14）。 在栅极和衬底（10）上沉积第一间隔层（20）。 沿着第一侧壁的第一间隔层的一部分形成第一间隔物（22）。 衬底层（30）沉积在栅极和衬底（10）上，并且第二间隔层（32）沉积在衬垫层（30）上。 第二间隔层（32）被蚀刻以留下第二间隔层（32）的一部分沿第一侧壁形成第二间隔物（34）。 还公开了半导体器件的金属栅极结构。

公开(公告)号：US20090148764A1

公开(公告)日：2009-06-11

申请号：US12257049

申请日：2008-10-23

申请人： Byung Sung Kwak ,  Nety M. Krishna ,  Kurt Eisenbelser ,  William J. Dauksher ,  Jon Candelaria

发明人： Byung Sung Kwak ,  Nety M. Krishna ,  Kurt Eisenbelser ,  William J. Dauksher ,  Jon Candelaria

IPC分类号： H01M6/18 ,  B05D5/12

CPC分类号： H01M10/0585 ,  H01M6/40 ,  H01M10/0436 ,  H01M10/052 ,  H01M2300/0068

摘要： Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.

摘要翻译： 提供了概念和方法，以通过消除和/或最小化常规物理（阴影）掩模的使用来降低薄膜电池（TFB）大批量制造的成本和复杂性。 激光划线和其他可选的物理无掩模图案化技术满足某些或所有图案化要求。 在一个实施例中，制造薄膜电池的方法包括提供衬底，在衬底上沉积与薄膜电池结构相对应的层，所述层按沉积顺序包括阴极，电解质和阳极，其中至少 沉积层中的一个在沉积期间由物理掩模未图案化，沉积保护涂层，以及划刻层和保护涂层。 此外，层的边缘可以被封装层覆盖。 此外，可以将这些层沉积在两个基板上，然后层压以形成薄膜电池。

公开(公告)号：US20050035381A1

公开(公告)日：2005-02-17

申请号：US10640856

申请日：2003-08-13

申请人： Paige Holm ,  Jon Candelaria

发明人： Paige Holm ,  Jon Candelaria

IPC分类号： H01L27/146 ,  H01L31/062

CPC分类号： H01L27/14643 ,  H01L27/1463 ,  H01L27/14636

摘要： An exemplary system and method for providing a vertically integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS layer (420); and a photosensing element (380) fabricated in a vertically integrated optically active layer (320, 350), where the optically active layer (320, 350) is bonded to the CMOS layer (420) and the optically active layer (320, 350) is positioned near a metalization surface (405) of the CMOS layer (420). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated photosensing components that may be readily incorporated with existing technologies for the improvement of CMOS imaging, device package form factors, weights and/or other manufacturing, device or material performance metrics.

摘要翻译： 公开了一种用于提供适合于在CMOS成像应用中使用的垂直集成光敏元件的示例性系统和方法，其特别包括：经处理的CMOS层（420）; 以及在垂直集成的光学有源层（320,350）中制造的光敏元件（380），其中光学活性层（320,350）被结合到CMOS层（420）和光学活性层（320,350） 位于CMOS层（420）的金属化表面（405）附近。 公开的特征和规格可以被不同地控制，配置，适配或以其他方式任意地修改，以进一步改善或以其它方式优化光敏性能或其它材料特性。 本发明的示例性实施例代表性地提供了可以容易地与现有技术结合以用于改进CMOS成像，设备封装外形，重量和/或其它制造，器件或材料性能度量的集成光敏元件。