公开(公告)号：US20050057975A1

公开(公告)日：2005-03-17

申请号：US10662188

申请日：2003-09-15

申请人： Jonathan Schmitt ,  Carol Gillies

发明人： Jonathan Schmitt ,  Carol Gillies

IPC分类号： G11C7/22 ,  H03L7/089 ,  H03L7/093 ,  G11C5/00

CPC分类号： G11C29/12015 ,  G11C7/22 ,  G11C7/222 ,  G11C29/028 ,  G11C29/50012 ,  H03L7/0893 ,  H03L7/093

摘要： A phase-locked loop within an integrated circuit assembly is provided. The phase-locked loop includes a plurality of subcells of semiconductor devices arranged in a base layer pattern on base layers of the integrated circuit assembly. One or more metal layers are formed over and interconnect the plurality of semiconductor devices in a metallization pattern. The phase-locked loop has an output frequency range that is changeable with a change to the metallization pattern without a corresponding change to the base layer pattern.

摘要翻译： 提供集成电路组件内的锁相环。 锁相环包括在集成电路组件的基极层上以基层图案布置的多个半导体器件子电池。 在金属化图案中形成多个金属层并在多个半导体器件上互连。 锁相环具有随着对金属化图案的改变而可改变的输出频率范围，而基本层图案没有相应的改变。

公开(公告)号：US08031506B2

公开(公告)日：2011-10-04

申请号：US12077888

申请日：2008-03-21

申请人： Jonathan Schmitt ,  Roy Carlson

发明人： Jonathan Schmitt ,  Roy Carlson

IPC分类号： G11C17/16

CPC分类号： G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse.

摘要翻译： 所公开的实施例是具有改进的IV特性的可编程存储器单元，其包括插入可编程薄氧化物反熔丝和厚氧化物存取晶体管之间的厚氧化物间隔晶体管。 间隔晶体管将在可编程反熔丝编程期间形成的断裂位置与存取晶体管分离，从而导致改进的IV特性。 可编程反熔丝靠近隔离晶体管的一侧，而存取晶体管靠近隔离晶体管的相对侧。 存取晶体管的源极区域耦合到地，并且存取晶体管的漏极区域也用作间隔晶体管的源极区域。 存取晶体管耦合到行线，而间隔晶体管和可编程反熔丝耦合到列线。 在编程期间通过将编程电压施加到可编程反熔丝来形成断裂位置。

公开(公告)号：US20100014340A1

公开(公告)日：2010-01-21

申请号：US12568430

申请日：2009-09-28

申请人： Myron Buer ,  Jonathan Schmitt ,  Laurentiu Vasiliu

发明人： Myron Buer ,  Jonathan Schmitt ,  Laurentiu Vasiliu

IPC分类号： G11C17/00 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C11/419 ,  G11C17/146 ,  G11C17/16

摘要： A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.

摘要翻译： 提供基于差分锁存器的一次可编程存储器单元。 基于差分锁存器的一次性可编程存储器单元包括差分锁存放大器，其具有耦合到第一输入端的第一组熔丝器件和耦合到第二输入端的第二组熔丝器件。 只能在存储单元中编写一组熔丝器件。 如果一组熔丝器件中的一个或多个保险丝器件被编程，则具有编程保险丝的一侧将在其对差分锁存放大器的输入端呈现较低的电压。 差分锁存放大器根据编程保险丝的一侧输出“0”或“1”。

公开(公告)号：US6130556A

公开(公告)日：2000-10-10

申请号：US98099

申请日：1998-06-16

申请人： Jonathan Schmitt ,  Gary Hom ,  Luong Hung

发明人： Jonathan Schmitt ,  Gary Hom ,  Luong Hung

IPC分类号： H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/00315

摘要： An integrated circuit buffer includes a core output terminal, a pad terminal, a pad pull-down transistor, a pad pull-up transistor, a pull-down control circuit and a pull-up control circuit. The pad pull-down transistor and the pad pull-up transistor are coupled to the pad terminal and have pull-up and pull-down control terminals, respectively. The pull-down control circuit is coupled between the core output terminal and the pull-down control terminal. The pull-up control circuit is coupled between the core output terminal and the pull-up control terminal. A pull-up voltage protection transistor is coupled in series between the pad pull-up transistor and the pad terminal and has a control terminal which is coupled to the pad terminal through a voltage feedback circuit.

摘要翻译： 集成电路缓冲器包括核心输出端子，焊盘端子，焊盘下拉晶体管，焊盘上拉晶体管，下拉控制电路和上拉控制电路。 焊盘下拉晶体管和焊盘上拉晶体管分别耦合到焊盘端子并具有上拉和下拉控制端子。 下拉控制电路耦合在核心输出端子和下拉控制端子之间。 上拉控制电路耦合在核心输出端子和上拉控制端子之间。 上拉电压保护晶体管串联在焊盘上拉晶体管和焊盘端子之间，并且具有通过电压反馈电路耦合到焊盘端子的控制端子。

公开(公告)号：US5977574A

公开(公告)日：1999-11-02

申请号：US829520

申请日：1997-03-28

申请人： Jonathan Schmitt ,  Timothy V. Statz

发明人： Jonathan Schmitt ,  Timothy V. Statz

IPC分类号： H01L21/82 ,  H01L27/118

CPC分类号： H01L27/11807

摘要： An arrangement and method for making a gate array architecture locates the well taps at the outer corners of each gate cell. The power buses are also located at the outside of the gate cell as well, enabling sharing of the well taps and the power buses. The location of the well taps at the outside corners of the standard cell reduces the number of transistors in a single repeatable cell from eight transistors to four transistors.

摘要翻译： 用于制造门阵列结构的布置和方法将阱抽头定位在每个栅极单元的外角处。 电力总线也位于门电池的外部，能够共享井口和电力总线。 在标准单元的外角处的阱抽头的位置将单个可重复单元中的晶体管的数量从八个晶体管减少到四个晶体管。

公开(公告)号：US08405435B2

公开(公告)日：2013-03-26

申请号：US10985289

申请日：2004-11-10

申请人： Jonathan Schmitt ,  Roger L. Roisen

发明人： Jonathan Schmitt ,  Roger L. Roisen

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/095

摘要： A delay locked loop generates a voltage on a common node as a function of a phase difference between a reference input and a feedback input. A first voltage-controlled delay line coupled between the reference input and the feedback input and has a first delay, which is controlled by the voltage on the common node. A second voltage-controlled delay line is selectively coupled in series with the first delay line, between the reference input and the feedback input, as a function of a test control input. The second delay line has a second delay, which is controlled by the voltage on the common node.

摘要翻译： 延迟锁定环路作为参考输入和反馈输入之间的相位差的函数在公共节点上产生电压。 耦合在参考输入和反馈输入之间的第一电压控制延迟线，并且具有由公共节点上的电压控制的第一延迟。 作为测试控制输入的函数，第二电压控制延迟线与参考输入和反馈输入之间的第一延迟线选择性地耦合。 第二延迟线具有由公共节点上的电压控制的第二延迟。

公开(公告)号：US20110255327A1

公开(公告)日：2011-10-20

申请号：US13173149

申请日：2011-06-30

申请人： Jonathan Schmitt

发明人： Jonathan Schmitt

IPC分类号： G11C17/08 ,  G11C17/00

CPC分类号： H01L27/105 ,  G11C8/12 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by applying a high voltage to a gate terminal of the bitcells, where the programming burns a conductive hole in an oxide layer above a higher threshold voltage layer in a memory device. The bitcells may comprise an oxide layer and a doped channel, which may comprise a plurality of different threshold voltage layers. The plurality of different threshold voltage layers may comprise at least one layer with a higher threshold voltage and at least one layer with a lower threshold voltage. The oxide may comprise a gate oxide. The bitcell may comprise an anti-fuse device. The layer with a higher threshold voltage may be separated from an output terminal of the bitcell by the at least one layer with a lower threshold voltage.

摘要翻译： 公开了用于分离阈值电压可编程比特单元的方法和系统，并且可以包括通过向位单元的栅极端施加高电压来选择性地对存储器件中的位单元进行编程，其中编程将氧化层中的导电孔烧在高于高阈值电压 层在内存设备中。 位单元可以包括氧化层和掺杂沟道，其可以包括多个不同的阈值电压层。 多个不同阈值电压层可以包括具有较高阈值电压的至少一个层和具有较低阈值电压的至少一个层。 氧化物可以包括栅极氧化物。 位单元可以包括反熔丝器件。 具有较高阈值电压的层可以与具有较低阈值电压的至少一个层与位单元的输出端分离。

公开(公告)号：US07609578B2

公开(公告)日：2009-10-27

申请号：US11933073

申请日：2007-10-31

申请人： Myron Buer ,  Jonathan Schmitt ,  Laurentiu Vasiliu

发明人： Myron Buer ,  Jonathan Schmitt ,  Laurentiu Vasiliu

IPC分类号： G11C17/18

CPC分类号： G11C17/18 ,  G11C11/419 ,  G11C17/146 ,  G11C17/16

摘要： A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell.

摘要翻译： 提供了基于四位SRAM的一次性可编程存储单元。 在编程之前，存储单元作为SRAM存储单元工作。 在编程之后，存储器单元作为一次性可编程非易失性存储单元工作。 存储单元包括在第一侧耦合到第一上保险丝和第一下熔丝的存储元件，并且在第二侧耦合到第二上保险丝和第二下保险丝。 当第一上保险丝和第二下保险丝被编程时，存储元件输出第一值。 当第二上保险丝和第一下保险丝被编程时，存储元件输出第二值。 编程后，上保险丝作为上拉保险丝，下保险丝作为下拉保险丝保持电池的状态。

公开(公告)号：US20090237975A1

公开(公告)日：2009-09-24

申请号：US12077888

申请日：2008-03-21

申请人： Jonathan Schmitt ,  Roy Carlson

发明人： Jonathan Schmitt ,  Roy Carlson

IPC分类号： G11C17/16

CPC分类号： G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse.

摘要翻译： 所公开的实施例是具有改进的IV特性的可编程存储器单元，其包括插入可编程薄氧化物反熔丝和厚氧化物存取晶体管之间的厚氧化物间隔晶体管。 间隔晶体管将在可编程反熔丝编程期间形成的断裂位置与存取晶体管分离，从而导致改进的IV特性。 可编程反熔丝靠近隔离晶体管的一侧，而存取晶体管靠近隔离晶体管的相对侧。 存取晶体管的源极区域耦合到地，并且存取晶体管的漏极区域也用作间隔晶体管的源极区域。 存取晶体管耦合到行线，而间隔晶体管和可编程反熔丝耦合到列线。 在编程期间通过将编程电压施加到可编程反熔丝来形成断裂位置。

公开(公告)号：US07129690B1

公开(公告)日：2006-10-31

申请号：US11321747

申请日：2005-12-29

申请人： Jonathan Schmitt ,  Steve Wurzer

发明人： Jonathan Schmitt ,  Steve Wurzer

IPC分类号： G01R23/12 ,  G01R23/175 ,  G06F1/04

CPC分类号： G06F1/04

摘要： The present invention provides a system and method for monitoring a short clock cycle on a semiconductor chip. The system includes a phase-locked loop (PLL) for receiving a reference clock as input and for outputting a PLL clock out. The system includes a delay-locked loop (DLL) for receiving the PLL clock out as input and for outputting a DLL phase offset clock. The DLL is locked to a frequency of the PLL clock out. The system may include an edge comparator for receiving the PLL clock out and the DLL phase offset clock as input. The edge comparator is suitable for monitoring each edge of the PLL clock out and each edge of the DLL phase offset clock, and for reporting a short clock cycle when an edge of the PLL clock out comes before an edge of the DLL phase offset clock.

摘要翻译： 本发明提供一种用于监视半导体芯片上的短时钟周期的系统和方法。 该系统包括用于接收参考时钟作为输入并用于输出PLL时钟输出的锁相环（PLL）。 该系统包括用于接收作为输入的PLL时钟输出和用于输出DLL相位偏移时钟的延迟锁定环（DLL）。 DLL被锁定到PLL时钟的频率。 该系统可以包括用于接收PLL时钟输出的边沿比较器和作为输入的DLL相位偏移时钟。 边沿比较器适用于监视PLL时钟输出的每个边沿和DLL相位偏移时钟的每个边沿，并且当PLL时钟输出的边沿在DLL相位偏移时钟的边沿之前报告短时钟周期。