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    Microelectronic devices using sacrificial layers and structures fabricated by same
    7.
    发明授权
    Microelectronic devices using sacrificial layers and structures fabricated by same 有权
    使用牺牲层的微电子器件和由其制造的结构

    公开(公告)号：US07612359B2

    公开(公告)日：2009-11-03

    申请号：US11860674

    申请日：2007-09-25

    申请人： Suk-Hun Choi ,  Yoon-Ho Son ,  Sung-Lae Cho ,  Joon-Sang Park

    发明人： Suk-Hun Choi ,  Yoon-Ho Son ,  Sung-Lae Cho ,  Joon-Sang Park

    IPC分类号： H01L29/02

    CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

    摘要： A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.

    摘要翻译： 在微电子基板的区域上形成介电层。 在电介质层上形成牺牲层，去除牺牲层和电介质层的部分以形成露出该区域的一部分的开口。 在牺牲层和开口中形成导电层。 去除部分牺牲层和电介质层上的导电层，以在电介质层中留下导电插塞并与该区域接触。 消除牺牲层和电介质层上的导电层的部分可以包括抛光以暴露牺牲层并在牺牲层和电介质层中留下导电插塞，蚀刻牺牲层以暴露电介质层并留下 导电插头从电介质层突出的部分，并且抛光以去除导电插塞的突出部分。 还讨论了通过这种技术形成的相变存储器件。

    Method of forming self-aligned double pattern
    8.
    发明授权
    Method of forming self-aligned double pattern 有权
    形成自对准双重图案的方法

    公开(公告)号：US07531456B2

    公开(公告)日：2009-05-12

    申请号：US11602270

    申请日：2006-11-21

    申请人： Byoung-Ho Kwon ,  Se-Rah Yun ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Joon-Sang Park

    发明人： Byoung-Ho Kwon ,  Se-Rah Yun ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Joon-Sang Park

    IPC分类号： H01L21/44

    CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  Y10S438/925

    摘要： Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.

    摘要翻译： 用于形成图案或沟槽的掩模图案可以包括可以通过典型的光刻工艺形成的第一掩模图案和可以在相邻的第一掩模图案之间以自对准方式形成的第二掩模图案。 牺牲层可以沉积并平坦化，使得第一掩模图案的顶部和第二掩模图案具有平坦表面。 在牺牲层的平坦化之后，剩余的牺牲层可以通过灰化处理去除。

    PHASE CHANGE MEMORY ELEMENTS HAVING A CONFINED PORTION OF PHASE CHANGE MATERIAL ON A RECESSED CONTACT
    9.
    发明申请
    PHASE CHANGE MEMORY ELEMENTS HAVING A CONFINED PORTION OF PHASE CHANGE MATERIAL ON A RECESSED CONTACT 失效
    相位变化记忆元件的相变元件

    公开(公告)号：US20080230762A1

    公开(公告)日：2008-09-25

    申请号：US12113846

    申请日：2008-05-01

    申请人： Joon-sang Park ,  Chang-ki Hong ,  Sang-yong Kim

    发明人： Joon-sang Park ,  Chang-ki Hong ,  Sang-yong Kim

    IPC分类号： H01L45/00

    CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

    摘要： Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall comprising a portion of the insulating layer by selectively etching a surface of the lower electrode relative to the insulating layer. A phase change memory layer is formed on the lower electrode. The phase change memory layer has a portion confined by the recess and surrounded by the insulating layer. An upper electrode is formed on the phase change memory layer. Phase change memory elements are also provided.

    摘要翻译： 制造相变存储元件的方法包括在半导体衬底上形成绝缘层，形成穿透绝缘层的通孔，在通孔中形成下电极，并通过选择性地形成具有侧壁的凹部，该侧壁包括绝缘层的一部分 相对于绝缘层蚀刻下电极的表面。 在下电极上形成相变存储层。 相变存储层具有被凹部限制并被绝缘层包围的部分。 在相变存储层上形成上电极。 还提供相变存储元件。

    Method of forming self-aligned double pattern
    10.
    发明申请
    Method of forming self-aligned double pattern 有权
    形成自对准双重图案的方法

    公开(公告)号：US20070148968A1

    公开(公告)日：2007-06-28

    申请号：US11602270

    申请日：2006-11-21

    申请人： Byoung-Ho Kwon ,  Se-Rah Yun ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Joon-Sang Park

    发明人： Byoung-Ho Kwon ,  Se-Rah Yun ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Joon-Sang Park

    IPC分类号： H01L21/44

    CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  Y10S438/925

    摘要： Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.

    摘要翻译： 用于形成图案或沟槽的掩模图案可以包括可以通过典型的光刻工艺形成的第一掩模图案和可以在相邻的第一掩模图案之间以自对准方式形成的第二掩模图案。 牺牲层可以沉积并平坦化，使得第一掩模图案的顶部和第二掩模图案具有平坦表面。 在牺牲层的平坦化之后，剩余的牺牲层可以通过灰化处理去除。