公开(公告)号：US08599635B2

公开(公告)日：2013-12-03

申请号：US13205966

申请日：2011-08-09

申请人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

发明人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

IPC分类号： G11C17/18

CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C29/04

摘要： A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.

摘要翻译： 熔丝电路包括程序单元，感测单元和控制单元。 程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。 感测单元包括具有基于控制信号而变化的电阻的可变电阻器单元，并且基于可变电阻器单元的电阻和程序输出信号产生感测输出信号。 控制单元产生具有根据操作模式改变的值的控制信号，并且基于感测输出信号执行关于节目单元的验证操作以产生验证结果。 程序单元可以基于验证结果重新编程。

公开(公告)号：US08514648B2

公开(公告)日：2013-08-20

申请号：US13051998

申请日：2011-03-18

申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

IPC分类号： G11C17/18

CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

公开(公告)号：US20120051164A1

公开(公告)日：2012-03-01

申请号：US13219998

申请日：2011-08-29

申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Ju-Seop Park

发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Ju-Seop Park

IPC分类号： G11C29/04 ,  H01L21/336 ,  G11C7/00 ,  H01L27/088

CPC分类号： G11C11/405 ,  G11C17/16 ,  G11C17/165 ,  H01L27/101 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/7835

摘要： A memory cell includes a selection transistor on a substrate and an antifuse on the substrate. The selection transistor includes a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source region connected to a bit line, and a first drain region, an impurity concentration of the first drain region being lower than an impurity concentration of the first source region. The antifuse includes a first electrode connected to a program word line and a second electrode connected to the selection transistor.

摘要翻译： 存储单元包括衬底上的选择晶体管和衬底上的反熔丝。 选择晶体管包括连接到读字线的第一栅极，将第一栅极与衬底绝缘的第一栅极绝缘层，连接到位线的第一源极区域和第一漏极区域，第一漏极区域的杂质浓度 漏极区域低于第一源极区域的杂质浓度。 反熔丝包括连接到编程字线的第一电极和连接到选择晶体管的第二电极。

公开(公告)号：US08848475B2

公开(公告)日：2014-09-30

申请号：US13219749

申请日：2011-08-29

申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Hyuck-Chai Jung ,  Ju-Seop Park

发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Hyuck-Chai Jung ,  Ju-Seop Park

IPC分类号： G11C17/18 ,  G11C17/16 ,  H01L27/10 ,  H01L23/525

CPC分类号： H01L27/101 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse circuit includes a program unit and a sensing unit. The program unit is programmed in response to a program signal and outputs a program output signal in response to a sensing enable signal. The sensing unit outputs a sensing output signal based on the program output signal and the sensing output signal indicates whether the program unit is programmed or not. The program unit includes an anti-fuse cell, a selection transistor, a program transistor and a sensing transistor. The anti-fuse cell includes at least two anti-fuse elements which are connected in parallel and are respectively broken down at different levels of a program voltage.

摘要翻译： 熔丝电路包括程序单元和感测单元。 程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。 感测单元基于程序输出信号输出感测输出信号，并且感测输出信号指示程序单元是否被编程。 程序单元包括反熔丝单元，选择晶体管，程序晶体管和感测晶体管。 反熔丝单元包括至少两个并联连接的反熔丝元件，并分别以不同的编程电压电平分解。

公开(公告)号：US08547763B2

公开(公告)日：2013-10-01

申请号：US13219998

申请日：2011-08-29

申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Ju-Seop Park

发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Ju-Seop Park

IPC分类号： G11C7/00 ,  G11C11/405

CPC分类号： G11C11/405 ,  G11C17/16 ,  G11C17/165 ,  H01L27/101 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/7835

摘要： A memory cell includes a selection transistor on a substrate and an antifuse on the substrate. The selection transistor includes a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source region connected to a bit line, and a first drain region, an impurity concentration of the first drain region being lower than an impurity concentration of the first source region. The antifuse includes a first electrode connected to a program word line and a second electrode connected to the selection transistor.

摘要翻译： 存储单元包括衬底上的选择晶体管和衬底上的反熔丝。 选择晶体管包括连接到读字线的第一栅极，将第一栅极与衬底绝缘的第一栅极绝缘层，连接到位线的第一源极区域和第一漏极区域，第一漏极区域的杂质浓度 漏极区域低于第一源极区域的杂质浓度。 反熔丝包括连接到编程字线的第一电极和连接到选择晶体管的第二电极。

公开(公告)号：US20130286759A1

公开(公告)日：2013-10-31

申请号：US13461987

申请日：2012-05-02

申请人： Ju-Seop Park ,  Jong-Pil Son ,  Sin-Ho Kim ,  Hyoung-Joo Kim ,  Je-Min Ryu ,  Sung-Min Seo

发明人： Ju-Seop Park ,  Jong-Pil Son ,  Sin-Ho Kim ,  Hyoung-Joo Kim ,  Je-Min Ryu ,  Sung-Min Seo

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C17/16 ,  G11C8/10 ,  G11C17/18 ,  G11C29/027

摘要： For selecting anti-fuses in a semiconductor memory device, a decoder block may be enabled to receive selection information for selecting the anti-fuses. The selection information is decoded in the decoder block to select at least one of the anti-fuses. Target operation is performed on the selected anti-fuses. The decoder block is disabled.

摘要翻译： 为了在半导体存储器件中选择抗熔丝，可以使解码器块接收用于选择抗熔丝的选择信息。 选择信息在解码器块中解码以选择至少一个抗熔丝。 对选定的防熔丝执行目标操作。 解码器块被禁用。

公开(公告)号：US08804448B2

公开(公告)日：2014-08-12

申请号：US13461987

申请日：2012-05-02

申请人： Ju-Seop Park ,  Jong-Pil Son ,  Sin-Ho Kim ,  Hyoung-Joo Kim ,  Je-Min Ryu ,  Sung-Min Seo

发明人： Ju-Seop Park ,  Jong-Pil Son ,  Sin-Ho Kim ,  Hyoung-Joo Kim ,  Je-Min Ryu ,  Sung-Min Seo

IPC分类号： G11C7/00

CPC分类号： G11C17/16 ,  G11C8/10 ,  G11C17/18 ,  G11C29/027

摘要： For selecting anti-fuses in a semiconductor memory device, a decoder block may be enabled to receive selection information for selecting the anti-fuses. The selection information is decoded in the decoder block to select at least one of the anti-fuses. Target operation is performed on the selected anti-fuses. The decoder block is disabled.

摘要翻译： 为了在半导体存储器件中选择抗熔丝，可以使解码器块接收用于选择抗熔丝的选择信息。 选择信息在解码器块中解码以选择至少一个抗熔丝。 对选定的防熔丝执行目标操作。 解码器块被禁用。

公开(公告)号：US09786387B2

公开(公告)日：2017-10-10

申请号：US14729295

申请日：2015-06-03

申请人： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Jong-Pil Son ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Jong-Pil Son ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： G06F11/10 ,  G11C29/00 ,  G11C29/52 ,  G11C11/15 ,  G11C29/04 ,  G11C29/44

CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C11/15 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/702 ,  G11C2029/0411 ,  G11C2029/4402

摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

公开(公告)号：US09070465B2

公开(公告)日：2015-06-30

申请号：US13586973

申请日：2012-08-16

申请人： Jong-Pil Son ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hyun-Ho Choi

发明人： Jong-Pil Son ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hyun-Ho Choi

IPC分类号： G11C11/00 ,  G11C11/16

CPC分类号： G11C11/161 ,  G11C11/1659 ,  G11C11/1673

摘要： An anti-fuse circuit includes an array of anti-fuses. Each anti-fuse has a tunneling magneto-resistance (TMR) element series connected with a transistor, such that breakdown of a magnetic tunnel junction (MTJ) in response to an applied first voltage stores fuse information. A sensing circuit senses and amplifies respective output signals provided by the anti-fuses.

摘要翻译： 反熔丝电路包括一组抗熔丝。 每个反熔丝具有与晶体管连接的隧道磁阻（TMR）元件串联，使得响应于施加的第一电压的磁隧道结（MTJ）的击穿存储熔丝信息。 感测电路感测并放大由防熔丝提供的各自的输出信号。

公开(公告)号：US09165637B2

公开(公告)日：2015-10-20

申请号：US13720998

申请日：2012-12-19

申请人： Sang-Yun Kim ,  Jong-Pil Son ,  Su-A Kim ,  Chul-Woo Park ,  Hong-Sun Hwang

发明人： Sang-Yun Kim ,  Jong-Pil Son ,  Su-A Kim ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC分类号： G11C29/00 ,  G11C11/406

CPC分类号： G11C11/40615 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/408 ,  G11C11/4096 ,  G11C2211/4061

摘要： A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

摘要翻译： 操作易失性存储器件的方法包括存储弱单元行的地址信息。 根据一些示例，在写入弱单元行之后，在预定时间内对弱单元行执行刷新操作。 根据一些示例，可以以对正常单元行的写恢复时间更长的写恢复时间来执行对弱单元行的写入操作。