公开(公告)号：US08564317B2

公开(公告)日：2013-10-22

申请号：US12719267

申请日：2010-03-08

Applicant: Jong-Won Han ,  Seok Goh ,  Byoung-Jun Min ,  Jung-Hyeon Kim ,  Sang-Sik Lee ,  Bo-Woo Kim ,  Ho-Jeong Choi

Inventor： Jong-Won Han ,  Seok Goh ,  Byoung-Jun Min ,  Jung-Hyeon Kim ,  Sang-Sik Lee ,  Bo-Woo Kim ,  Ho-Jeong Choi

IPC: G01R31/00

CPC classification number: G01R1/0458 ,  G01R31/2863 ,  G01R31/2875

Abstract: A test socket is provided that includes a socket body to receive an object to be tested, a lid disposed on the socket body, one or more pushers coupled to a first surface of lid to apply force to a first surface of the object toward the socket body, and a temperature controlling member to provide a temperature to the object. A semiconductor package may be tested in a test apparatus that includes the test socket, the methods of testing including receiving a semiconductor package in a socket in a test chamber, applying a first temperature to the test chamber to test the semiconductor package at a first test temperature, and applying a second temperature to the semiconductor package to test the semiconductor package at a second test temperature by controlling the application of the second temperature with the socket.

Abstract translation: 提供了一种测试插座，其包括用于接收被测试对象的插座主体，设置在插座主体上的盖子，一个或多个连接到盖的第一表面的推动器，以向该插座的第一表面施加力 主体和温度控制构件以向对象提供温度。 可以在包括测试插座的测试设备中测试半导体封装，测试方法包括在测试室中的插座中接收半导体封装，将第一温度施加到测试室以在第一测试中测试半导体封装 温度，并且向半导体封装施加第二温度以通过控制第二温度与插座的应用来在第二测试温度下测试半导体封装。

公开(公告)号：US20120088077A1

公开(公告)日：2012-04-12

申请号：US13239928

申请日：2011-09-22

Applicant: Hyun-Jung JUNG ,  Chang-Youn HWANG ,  Hoon-Soo PARK ,  Jung-Hyeon KIM

Inventor： Hyun-Jung JUNG ,  Chang-Youn HWANG ,  Hoon-Soo PARK ,  Jung-Hyeon KIM

IPC: B32B3/10 ,  B05D5/02 ,  B32B27/00

CPC classification number: B05D7/04 ,  B05D5/06 ,  B05D7/56 ,  Y10T428/24851 ,  Y10T428/24868

Abstract: An injection preform having a pattern on a surface thereof and realizing a transparent pattern paint layer for forming a crack pattern in a transparent or semi-transparent substrate, and a method of manufacturing the same. The injection preform preferably includes: a substrate injection molded so as to be transparent or semi-transparent; a primer layer painted on a rear surface of the substrate; a transparent pattern paint layer painted on a rear surface of the primer layer, a surface of the transparent pattern paint layer being dried with hot air in an oven such that a pattern is formed; a deposition layer deposited on a rear surface of the transparent pattern paint layer; a finishing layer painted on a rear surface of the deposition layer; and a clear coating layer painted on a front surface of the substrate.

Abstract translation: 一种在其表面上具有图案并且实现在透明或半透明基板中形成裂纹图案的透明图案涂料层的注射成型体及其制造方法。 注射成型体优选包括：注射成型为透明或半透明的基底; 涂布在基板的后表面上的底漆层; 涂布在底漆层的背面上的透明图案涂料层，透明图案涂料层的表面在烘箱中用热风干燥，形成图案; 沉积在所述透明图案涂料层的后表面上的沉积层; 涂覆在沉积层的后表面上的整理层; 以及涂布在基板的前表面上的透明涂层。

公开(公告)号：US07869188B2

公开(公告)日：2011-01-11

申请号：US11998132

申请日：2007-11-28

Applicant: Keun-Bong Lee ,  Jung-Hyeon Kim

Inventor： Keun-Bong Lee ,  Jung-Hyeon Kim

IPC: H01G4/005 ,  H01G4/06

CPC classification number: H01G4/012 ,  H01G4/005 ,  H01G4/236 ,  H01G4/30

Abstract: A capacitor structure includes an insulating layer, first conductive patterns, second conductive patterns, an insulating interlayer, third conductive patterns, and fourth conductive patterns. The first and second conductive patterns are alternately arranged on the insulating layer to be spaced apart from one another. The first and second conductive patterns have side faces where concave portions and convex portions are formed. The insulating interlayer is formed on the insulating layer to cover the first and second conductive patterns. The third and fourth conductive patterns are alternately arranged on the insulating interlayer to be spaced apart from one another. The third and fourth conductive patterns have side faces where concave portions and convex portions are formed.

Abstract translation: 电容器结构包括绝缘层，第一导电图案，第二导电图案，绝缘夹层，第三导电图案和第四导电图案。 第一和第二导电图案交替地布置在绝缘层上以彼此间隔开。 第一和第二导电图案具有形成凹部和凸部的侧面。 在绝缘层上形成绝缘中间层以覆盖第一和第二导电图案。 第三和第四导电图案交替地布置在绝缘中间层上以彼此间隔开。 第三和第四导电图案具有形成凹部和凸部的侧面。

公开(公告)号：US07830599B2

公开(公告)日：2010-11-09

申请号：US12164571

申请日：2008-06-30

Applicant: Jong-soo Lee ,  Kee-uk Jeon ,  Kwan-heung Kim ,  Jung-hyeon Kim

Inventor： Jong-soo Lee ,  Kee-uk Jeon ,  Kwan-heung Kim ,  Jung-hyeon Kim

IPC: G03B21/56 ,  B29D11/00

CPC classification number: H04N9/3144 ,  H04N9/3114

Abstract: A projection-type display apparatus and a display method thereof are disclosed, the projection-type display apparatus including a coated portion which is formed on a surface of a substrate, and which scans a video onto a screen, and a patterned portion which is formed on another surface of the substrate in a serrated pattern, wherein the serrated pattern is formed on the substrate according to the surface area of the patterned portion and the depth of the serrated pattern. A serrated pattern is formed on a substrate forming a reflective portion to reflect a video on a screen, so the cooling surface area of the substrate is increased, thereby compensating for distortions in video scanned onto the screen.

Abstract translation: 公开了一种投影式显示装置及其显示方法，该投影型显示装置包括形成在基板的表面上并将视频扫描到屏幕上的涂布部分和形成的图案部分 在锯齿状图案的基板的另一表面上，其中根据图案部分的表面积和锯齿形图案的深度，在基底上形成锯齿形图案。 在形成反射部分的基板上形成锯齿形图案以将视频反射在屏幕上，从而增加了基板的冷却表面积，从而补偿了扫描到屏幕上的视频失真。

公开(公告)号：US20100248460A1

公开(公告)日：2010-09-30

申请号：US12659959

申请日：2010-03-26

Applicant: Jin-Il Lee ,  Urazaev Vladimir ,  Jin-Ha Jeong ,  Seung-Back Shin ,  Sung-Lae Cho ,  Hyeong-Geun An ,  Dong-Hyun Im ,  Jung-Hyeon Kim

Inventor： Jin-Il Lee ,  Urazaev Vladimir ,  Jin-Ha Jeong ,  Seung-Back Shin ,  Sung-Lae Cho ,  Hyeong-Geun An ,  Dong-Hyun Im ,  Jung-Hyeon Kim

IPC: H01L21/365 ,  H01L21/469 ,  H01L21/443 ,  H01L21/465

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1683

Abstract: A method of forming an information storage pattern, includes placing a semiconductor substrate in a process chamber, injecting first, second and third process gases into the process chamber during a first process to form a lower layer on the substrate based on a first injection time and/or a first pause time, injecting the second process gas into the process chamber during a second process, wherein the second process gas is injected into the process chamber during a first elimination time, injecting a fourth process gas together with the second and third process gases into the process chamber during a third process in accordance with a second injection time and/or a second pause time to form an upper layer on the lower layer, and injecting the second process gas into the process chamber during a fourth process, wherein the second process gas is injected into the process chamber during a second elimination.

Abstract translation: 一种形成信息存储图案的方法，包括将半导体衬底放置在处理室中，在第一过程中将第一，第二和第三处理气体注入到处理室中，以在第一注入时间基底上形成下层;以及 /或第一暂停时间，在第二过程期间将第二处理气体注入处理室，其中第二处理气体在第一消除时间期间被注入到处理室中，与第二和第三处理一起喷射第四处理气体 根据第二喷射时间和/或第二暂停时间，在第三过程期间将气体进入处理室，以在下层形成上层，并且在第四过程期间将第二处理气体注入到处理室中，其中， 在第二次消除期间将第二工艺气体注入到处理室中。

公开(公告)号：US20100248442A1

公开(公告)日：2010-09-30

申请号：US12731637

申请日：2010-03-25

Applicant: Jin-Il Lee ,  Urazaev Vladimir ,  Jin-Ha Jeong ,  Seung-Back Shin ,  Sung-Lae Cho ,  Hyeong-Geun An ,  Dong-Hyun Im ,  Young-Lim Park ,  Jung-Hyeon Kim

Inventor： Jin-Il Lee ,  Urazaev Vladimir ,  Jin-Ha Jeong ,  Seung-Back Shin ,  Sung-Lae Cho ,  Hyeong-Geun An ,  Dong-Hyun Im ,  Young-Lim Park ,  Jung-Hyeon Kim

IPC: H01L21/02

CPC classification number: H01L45/1616 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

Abstract: Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.

Abstract translation: 提供形成相变存储器件的方法。 可以制备具有下电极和层间绝缘层的半导体器件。 下电极可以被层间绝缘层包围。 可以将源气体，反应气体和吹扫气体注入到半导体制造装置的处理室中，以在半导体衬底上形成相变材料层。 源气体可以同时注入到处理室中。 相变材料层可以通过层间绝缘层与下电极接触。 可以蚀刻相变材料层以在层间绝缘层中形成相变存储单元。 可以在相变存储单元上形成上电极。

公开(公告)号：US07778008B2

公开(公告)日：2010-08-17

申请号：US11983991

申请日：2007-11-13

Applicant: Keun-Bong Lee ,  Jung-Hyeon Kim

Inventor： Keun-Bong Lee ,  Jung-Hyeon Kim

IPC: H01G4/005 ,  H01G4/06

CPC classification number: H01G4/005 ,  H01G4/012 ,  H01G4/30 ,  Y10T29/435

Abstract: In a capacitor structure and a method of manufacturing the capacitor structure, first and second conductive patterns are formed on a substrate. The first and second conductive patterns extend in a first direction. The first and second conductive patterns are alternately arranged to be spaced apart from one another in a second direction substantially perpendicular to the first direction. An insulating interlayer is formed on the substrate to cover the first and second conductive patterns. Third and fourth conductive patterns extending in a third direction lying at an angle of between about 0° and about 90° relative to the first direction are formed on the insulating interlayer. The third and fourth conductive patterns are alternately arranged to be spaced apart from one another in a fourth direction substantially perpendicular to the third direction.

Abstract translation: 在电容器结构和制造电容器结构的方法中，在基板上形成第一和第二导电图案。 第一和第二导电图案沿第一方向延伸。 第一和第二导电图案交替地布置成在基本上垂直于第一方向的第二方向上彼此间隔开。 在衬底上形成绝缘中间层以覆盖第一和第二导电图案。 在绝缘中间层上形成有相对于第一方向以约0°至约90°之间的角度在第三方向延伸的第三和第四导电图案。 第三和第四导电图案交替地布置成在基本上垂直于第三方向的第四方向上彼此间隔开。

公开(公告)号：US20100154130A1

公开(公告)日：2010-06-24

申请号：US12588454

申请日：2009-10-15

Applicant: Jeong Su Han ,  Ho Yoon ,  Jung Hyeon Kim ,  Hyen Young Choi ,  Sang Jun Lee ,  Jung Won Choi ,  O Do Ryu

Inventor： Jeong Su Han ,  Ho Yoon ,  Jung Hyeon Kim ,  Hyen Young Choi ,  Sang Jun Lee ,  Jung Won Choi ,  O Do Ryu

IPC: D06F33/00 ,  F16F9/36

CPC classification number: D06F39/003 ,  D06F37/203 ,  F16F7/09 ,  F16F9/3292 ,  F16F9/56 ,  F16F2230/08 ,  F16F2232/04

Abstract: A damper including a cylinder, a piston inserted in the cylinder, a movable member disposed in the piston to be movable in the cylinder in a length direction of the cylinder, and a weight sensor mounted on an inner surface of the cylinder, facing an end of the piston, to perceive weight loaded on the piston through contact with the movable member. When applied to a washing machine, the damper is capable of perceiving accurate weight of the laundry supplied in the washing machine.

Abstract translation: 一种阻尼器，包括：气缸，插入气缸中的活塞，设置在活塞中的可移动构件，以在气缸的长度方向上在气缸中移动;以及重量传感器，其安装在气缸的内表面上， 以感知通过与活动件接触而装载在活塞上的重量。 当应用于洗衣机时，阻尼器能够感知洗衣机中提供的衣物的精确重量。

公开(公告)号：US07715200B2

公开(公告)日：2010-05-11

申请号：US12232990

申请日：2008-09-26

Applicant: Jung-Chan Cho ,  Yang-Je Lee ,  Hyun-Seok Choi ,  Yong-Hyun Kim ,  Jung-Hyeon Kim ,  Hyo-Jae Bang ,  Do-Hyung Kim ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jae-Sang Baik ,  Yong-Jin Kim

Inventor： Jung-Chan Cho ,  Yang-Je Lee ,  Hyun-Seok Choi ,  Yong-Hyun Kim ,  Jung-Hyeon Kim ,  Hyo-Jae Bang ,  Do-Hyung Kim ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jae-Sang Baik ,  Yong-Jin Kim

IPC: H05K1/00

CPC classification number: H05K1/147 ,  H05K1/117 ,  H05K1/189 ,  H05K3/323 ,  H05K3/361 ,  H05K3/4691 ,  H05K2201/042 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/0949 ,  H05K2201/10159 ,  H05K2203/1572

Abstract: A stacked semiconductor module, a method of fabricating the same, and an electronic system using the module are provided. A first semiconductor module having a plurality of semiconductor devices mounted on a rigid printed circuit board (PCB) and a second semiconductor module having a plurality of other semiconductor devices mounted on a flexible PCB are provided. On the rigid PCB a number L of first tabs may be disposed on a first surface, and a number K of second tabs may be disposed on a second surface of the rigid PCB. The flexible PCB may have a number M of third tabs on a third surface, and a number N of fourth tabs on a fourth surface of the flexible PCB. The second tabs may be combined with the third tabs using a conductive adhesive. The third tabs may be electrically connected to corresponding ones of the second tabs.

Abstract translation: 提供堆叠半导体模块，其制造方法和使用该模块的电子系统。 提供了具有安装在刚性印刷电路板（PCB）上的多个半导体器件和具有安装在柔性PCB上的多个其它半导体器件的第二半导体模块的第一半导体模块。 在刚性PCB上，可以在第一表面上设置数L个第一突出部，并且可以在刚性PCB的第二表面上设置数个K个第二突片。 柔性PCB可以在第三表面上具有数量M的第三突出部，并且在柔性PCB的第四表面上可以具有数目N的第四突出部。 第二突片可以使用导电粘合剂与第三突片组合。 第三突片可以电连接到相应的第二突片。

公开(公告)号：US07656180B2

公开(公告)日：2010-02-02

申请号：US11937342

申请日：2007-11-08

Applicant: Jae-Nam Lee ,  Jung-Hyeon Kim ,  Ju-II Kang ,  Jin-Woo Yang

Inventor： Jae-Nam Lee ,  Jung-Hyeon Kim ,  Ju-II Kang ,  Jin-Woo Yang

IPC: G01R31/02

CPC classification number: G01R31/2817 ,  G01R31/2863

Abstract: A burn-in board connection device includes a first connection unit to hold a burn-in board and move in a first direction perpendicular to the burn-in board that is inserted in a chamber of a burn-in test device, a second connection unit to move in a second direction parallel to the burn-in board to attach/detach the burn-in board that is held by the first connection unit to/from a connector disposed in the chamber. A burn-in board connection method includes coupling a finger to the burn-in board by moving the finger in a first direction, attaching the burn-in board to a connector by moving the finger in a second direction, and driving the finger by converting a rotation of a servo motor into a linear movement of the finger.

Abstract translation: 老化板连接装置包括：第一连接单元，用于保持老化板并且沿垂直于插入老化测试装置的室中的老化板的第一方向移动;第二连接单元 沿平行于老化板的第二方向移动以将由第一连接单元保持的老化板与设置在腔室中的连接器相连接/分离。 老化板连接方法包括通过沿第一方向移动手指将手指连接到老化板，通过沿第二方向移动手指将老化板附接到连接器，并且通过转换来驱动手指 伺服电动机旋转到手指的线性运动。